LPDDR3 DRAM Evolution for Mobile Applications: Power & Performance Trends

1. IEE5011 – FALL 2013Memory SystemsLPDDR3 DRAM for Mobile Applications Balakumar Department of Electronics Engineering National Chiao Tung University balakumar.meirtt@gmail.com

2. Outline Motivation PC Like Performance Mobile DRAM Evolutionary Path LPDDRx (Across generations) LPDDR3 ISM (Inner Stack Memory Module) Comparison with Wide I/O Samsung LPDDR3 Conclusion

3. Motivation Energy efficiency is the major optimization criteria for systems-on-chip (SoCs) for mobile devices (smartphones and tablets). Performance and power consumption of DRAMs (LPDDRs) depends on the configuration of system level parameters, such as operating frequency, interference bandwidth, request size, and memory map.

4. What is PC-Like Memory Performance

5. Common PC Configurations

6. System Performance Trend (PC vs Smartphone)

7. Mobile DRAM Evolution

8. Future Mobile DRAM Positioning

9. MDRAM will Exceed PC DRAM Performance

10. Mobile DRAM Density Requirement

11. Memory PKG Trend for Smartphone Application

12. Mobile Application Thickness Trend

13. Low Power Memory - Today

14. Low Power DRAM- Features • Low Voltage • Low I/O Capacitance • Unterminated I/Os • Typically x16 orx32 data width per die • Multi-die packages • No DLL • Very Low Standby Power • Temperature Compensated in Standby mode • Deep Power Down mode • Partial Array Self- Refresh

15. Low Power LPDDR vs Low Voltage DDR3L DDR3L is a Lower Voltage version in PC DRAM LPDDR3 is used in Mobile Devices

16. LPDDR2 to LPDDR3 Migration • Increase bandwidth 50% LPDDR2-1066 - From 8.5GB/s to 12.8GB/s • Fast time-to market -Re-use existing LPDDR2 infrastructure - No change or limited changes to interface, command protocol, state machine, etc. - Only changes which enables higher speed operation should be considered. - SOC vendors and DRAM vendors should re-use as much as possible from LPDDR2 in order to meet very aggressive time-to-market.

17. LPDDR3-Key Features Comparison

18. LPDDR3-Addressing • Overlap between LPDDR2/3 at 4-8GB - Same addressing for maximum IP re-use from LPDDR2 • Additional 16GB & 32GB definitions - 32GB TBD- feasibility still to be determined. - 16GB addressing defined, but refresh requirements still TBD.

19. LPDDR3-Mobile Platform

20. LPDDR3-Power • LPDDR2 LPDDR3: no change in VDD • Larger Pre-fetch, higher R/W Power. • Faster tCK: Higher IO Power. Low-Power DRAM? - Power efficiency (pJ/bit) improvement with higher performance- performance increase out-gains power increase - 2-ch LPDDR2 delivers 8.3GB/sec at 533MHz, approx 11.9pJ/bit - 2-ch LPDDR3 delivers 12.8GB/sec at 800MHz, approx 9.2pJ/bit - Higher performance also allows for faster data transfer of fixed quantity resulting in longer idle time for additional power savings.

21. LPDDR3-Low Power Features • TCSR- same feature as LPDDR2 • PASR- same as LPDDR2 (identical bank & segment masking as S4) • DPD- supported • Power-down mode • Self-refresh mode • New Requirements - tCPDED required for PD/SREF/DPD entry - tMRRI required upon PD exit

22. LPDDR3-Low Power Mode Changes

23. LPDDR3-Memory Partitioning Concept

24. LPDDR3-System Design Considerations • Signal Integrity is significantly affected by these parameters. - CIO (capacitance) - Driver slew rate - Package design - Power delivery (key in PoP implementation) • Great care must be taken to design a system that has good signal integrity at 1600 MT/s with this PHY • It is highly recommended to work with memory vendors to model your system using extracted driver and package parameters. • Additional features can be employed to improve signal margin. - DQ on Die Termination (ODT) - Asym drive strength

25. LPDDR2 and LPDDR3 (PoP) • Package-on-Package offers low power and area • Compared to packaged parts on PCB, PoP can reduce power, area and volume - Short Paths with relatively good signal integrity properties. - Saves PCB area by using vertical direction. - May lead to thermal issues if fie underneath is generating heat

26. Challenges in Mobile DRAM Channel

27. ISM (Inner-Stack Memory Module)

28. 2-channel ISM design for LPDDR2/3

29. Understanding LPDDR3 and Wide I/O

30. Finding Ideal PCB Environment • Pop provides very short Electrical Connection for high speed and low power - Power dissipation is limited

31. SoC Construction

32. LPDDR3 vs Wide I/O

33. Samsung LPDDR3 Review

34. Gain exceptional design advantages Benefits of using Samsung Mobile DRAM in computing, consumer, and communication devices include: •Reduced power consumption in standby mode enabled by advanced, on-chip technologies such as temperature-compensated self-refresh (TCSR). • Extended battery life in operational mode with power consumption as low as 1.2V. • High operational speeds that keep pace with today´s fast mobile CPUs and large displays, enabling users to power through demanding applications and multitasking. • Design flexibility with a choice of thin, small form-factor packages that occupy very little board space.

35. Samsung LPDDR3 DRAM

36. Conclusion Future DRAM bandwidth will continue to increase Power is reduced in LPDDR3, but still proportional to bandwidth. Use multiple techniques to meet performance and power goals of high bandwidth low power DRAM.

37. Refrence Young-Chul Cho; Yong-Cheol Bae; Byoung-Mo Moon; Yoon-Joo Eom; Min-Su Ahn; Won Young Lee; Cheong-Ryong Cho; Min-Ho Park; Young-Jin Jeon; Jin-Oh Ahn; Baek-Kyu Choi;Dan-Kyu Kang; Sang-Hyuk Yoon; Yun-Seok Yang; Kwang-Il Park; Jung-Hwan Choi; Jung-Bae Lee; Joo-Sun Choi, "A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with LowVoltage-Swing Terminated Logic and adaptive calibration scheme for mobile application," VLSICircuits (VLSIC), 2013 Symposium on , vol., no., pp.C240,C241, 12-14 June 2013. A. B. Kahng and V. Srinivas, “Mobile System Considerations for SDRAM Interface Trends,” in Proc. SLIP, 2011. Nomura, T.; Mori, R.; Ito, M.; Takayanagi, K.; Ochiai, T.; Fukuoka, K.; Otsuga, K.; Nii, K.;Morita, S.; Hashimoto, T.; Kida, T.; Yamada, J.; Tanaka, H., "Testability improvement for 12.8 GB/s Wide IO DRAM controller by small area pre-bonding TSV tests and a 1 GHz sampled fully digital noise monitor," Custom Integrated Circuits Conference (CICC), 2013 IEEE , vol., no., pp.1,4, 22-25 Sept. 2013. Leibowitz, B, et al. “A 4.3 GB/s Mobile Memory Interface With Power-Efficient BW Scaling” IEEE JSSC, pp,889-898, Feb.2010. Weis, C.; Loi, I.; Benini, L.; Wehn, N., "Exploration and Optimization of 3-D Integrated DRAM Subsystems," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.32, no.4, pp.597,610, April 2013. Gomony, M.D.; Weis, C.; Akesson, B.; When, N.; Goossens, K., "DRAM selection and configuration for real-time mobile systems," Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012 , vol.,no., pp.51,56, 12-16 March 2012 doi: 10.1109/DATE.2012.6176432. “JEDEC Low Power Double Data Rate (LPDDR3) SDRAM Standard,” Sep 2011. “JEDEC Low Power Double Data Rate (LPDDR2) SDRAM Standard,” Dec 2010. “JEDEC Low Power Double Data Rate (LPDDR) SDRAM Standard,” Feb 2009.

38. Reference B. Akesson et al., “Memory Controllers for High-Performance and Real-Time MPSoCs,” in Proc. CODES+ISSS, 2011. JEDEC Standard Wide IO SDR specification. Dec. 2011. Y.C. Bae, et al. “A 1.2V 1.6Gb/s/pin 4Gb Low Power DDR3 SDRAM with Input Skew Calibration and Enhanced Refresh Control Schemes” IEEE ISSCC, pp. 44-45, Feb. 2012. Park, S.-S. et ai, "Integrated circuit package-inpackage system with side-by-side and offset packaging, US patentNo. US 7,812,435 B2. http://www.samsung.com/global/business/semiconductor/product/mobile-dram/overview. http://www.samsung.com/global/business/semiconductor/news-events/pressreleases/detail?newsId=12979. https://memorylink.samsung.com/ecomobile/mem/ecomobile/product/productOverview.do?topMenu=P&subMenu=mobileDram&partSetNo=LPDDR3&partSetLabel=LPDDR3.