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Belle II Silicon Vertex Detector. Your Name (Your Institute). Generic Slides. Belle II. Belle II SVD Layout. Geometry optimization is underway New central pixel double-layer using DEPFET Strip layers extend to r~14 cm
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Belle II Silicon Vertex Detector Your Name (Your Institute) Generic Slides Belle II
Belle II SVD Layout • Geometry optimization is underway • New central pixel double-layer using DEPFET • Strip layers extend to r~14 cm • Every sensor read out individually(no ganging) to maintain good S/N chip-on-sensor concept 4 layers of double-sided strip sensors Double-layer of DEPFET pixels Your Name
Origami – Chip-on-Sensor Concept • Chip-on-sensor concept for double-sided readout • Flex fan-out pieces wrapped to opposite side (hence “Origami“) • All chips aligned on one side single cooling pipe Side View (below) Your Name
Origami Module with 6” HPK DSSD Your Name
Sketch of the Outermost Ladder (Layer 6) • Center sensors have Origami structure, edge sensors are read out from sides • Averaged material budget over the full module: 0.58% X0 ca. 60cm Your Name
Carried by ribs made of carbon fiber and Airex foam Very stiff, yet lightweight thanks to the sandwich construction Ladder Mechanics Cooling Pipe Sensor Support Ribs Your Name
CO2 Cooling • Open (blow) system operated from a CO2battery exists • Stable operation at ~1 g/s mass flow for several days achieved during 2011 beam test at CERN • Front-end temperature -16°C (Origami modules) Your Name
Readout System • Prototype readout systemexists • Verified in several beam tests • Basis for future SVD system shown below Your Name
Prototype Readout System Repeater Box Level translation, buffering FADC+PROC (9U VME) Digitization, zero-suppression, hit time reconstruction Your Name
Finesse Transmitter Board (FTB) • Sends FADC data through optical link to • COPPER • Pixel system (Giessen box) • First boards are now being tested • Firmware to be developed Your Name
Occupancy Reduction Your Name
Origami Module (TDC error subtracted) Measured Hit Time Precision • Results achieved in beam tests with several different types of Belle DSSD prototype modules (covering a broad range of SNR) • 2...3 ns RMSaccuracy at typical cluster SNR(15...25) • Working onimplementationin FPGA (using lookup tables) – simulationsuccessful Your Name