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The Belle II Silicon Vertex Detector Readout Chain

TWEPP2012, 19 September 2012. The Belle II Silicon Vertex Detector Readout Chain. Markus Friedl (HEPHY Vienna). Introduction Front-End Junction Box FADC DAQ Summary. Introduction Front-End Junction Box FADC DAQ Summary. Belle. KEKB. Linac. KEKB and Belle @ KEK (1999-2010).

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The Belle II Silicon Vertex Detector Readout Chain

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  1. TWEPP2012, 19 September 2012 The Belle II Silicon Vertex Detector Readout Chain Markus Friedl (HEPHY Vienna)

  2. Introduction Front-End Junction Box FADC DAQ Summary M.Friedl (HEPHY Vienna): Belle II SVD Readout

  3. Introduction Front-End Junction Box FADC DAQ Summary M.Friedl (HEPHY Vienna): Belle II SVD Readout

  4. Belle KEKB Linac KEKB and Belle @ KEK (1999-2010) • Center of mass energy: Y(4S) (10.58 GeV) • High intensity beams (1.6 A & 1.3 A) • Integrated luminosity of 1 ab-1 recorded in total • Belle mentioned explicitly in 2008 Physics Nobel Prize announcement to Kobayashi and Masukawa • Asymmetric machine:8 GeVe- on 3.5 GeVe+ Belle KEKB ~1 km in diameter Linac About 60km northeast of Tokyo M.Friedl (HEPHY Vienna): Belle II SVD Readout

  5. Belle Detector (1999–2010) Aerogel Cherenkov counter n=1.015~1.030 SC solenoid 1.5 T 3.5 GeV e+ CsI(Tl) 16 X0 TOF counter Central Drift Chamber small cell +He/C2H5 8 GeV e- Si vertex detector 4 layers DSSD µ / KL detection 14/15 lyr. RPC+Fe M.Friedl (HEPHY Vienna): Belle II SVD Readout

  6. SuperKEKB/Belle II Upgrade: 2010–2015 • Aim: super-high luminosity ~81035 cm-2s-1  11010 BB / year • LoI published in 2004; TDR published in 2010 • Refurbishment of accelerator and detector required • nano-beams with cross-sections of ~10 µm x 60 nm • 10 mm radius beam pipe at interaction region http://belle2.kek.jp M.Friedl (HEPHY Vienna): Belle II SVD Readout

  7. Previous SVD Layout (until 2010) • 4 straight layers of 4" double-sided silicon detectors (DSSDs) • Outer radius ofr~8.8 cm • Up to three 4” sensors are daisy-chained and read out by one hybrid located outside of acceptance region (VA1 chip) M.Friedl (HEPHY Vienna): Belle II SVD Readout

  8. Belle Silicon Vertex Detector (SVD) • Previous SVD limitations were • occupancy (~10% in innermost layer)  need faster shaping • dead time (~3%)  need faster readout and pipeline • Belle II needs detector with • high background tolerance • pipelined readout • robust tracking • low material budget in active volume 10% Current SVD is not suitable for Belle II M.Friedl (HEPHY Vienna): Belle II SVD Readout

  9. New Layout for Belle II SVD (2015-) • New double-layer pixel detector using DEPFET technology • Four layers with 6” double-sided strip detectors and forward part • Optimized for precision vertex reconstruction of the decays of short-lived B-mesons 4 layers of double-sided strip sensors Two layers of DEPFET pixels M.Friedl (HEPHY Vienna): Belle II SVD Readout

  10. Sensor underneath flex circuit End ring (support) APV25 chips Origami ladder Pitch adapter bentaround sensor edge Cooling pipe M.Friedl (HEPHY Vienna): Belle II SVD Readout

  11. Readout Chain Overview • Analog APV25 readout is through copper cable to FADCs • Junction box provides LV to front-end Finesse Transmitter Board (FTB) FADC 1748APV25chips ~2mcoppercable Junctionbox ~10mcopper cable Unified opticaldata link (>20m) COPPER Front-endhybrids Rad-hardDC/DC converters Analog level translation,datasparsificationandhit time reconstruction Unified Belle IIDAQ system M.Friedl (HEPHY Vienna): Belle II SVD Readout

  12. Not Entirely New… • 2007: plans for an intermediate upgrade of Belle I SVD • Prototype system built and tested thoroughly in several beam tests since then • Now enlarging and improving details, but concept is same • See reports at previous TWEPPs for details & performance M.Friedl (HEPHY Vienna): Belle II SVD Readout

  13. Introduction Front-End Junction Box FADC DAQ Summary M.Friedl (HEPHY Vienna): Belle II SVD Readout

  14. APV25 Readout Chip • Developed for CMS (LHC) by IC London and RAL (70k chips installed) • 0.25 µm CMOS process (>100 MRad tolerant) • 40 MHz clock (adjustable), 128 channels • 192 cell analog pipeline no dead time • 50 ns shaping time low occupancy • Noise: 250 e + 36 e/pF  must minimize capacitive load!!! • Multi-peak mode (read out several samples along shaping curve) • Thinning to 100µm successful Schematics of one channel M.Friedl (HEPHY Vienna): Belle II SVD Readout

  15. Front-End Hybrids • 2 variants • Standard PCBs outside acceptance for the edge sensors • “Origami” chip-on-sensor concept for inner sensors See presentation by C. Irmler today at 14:50 Martin Wood Lecture Theater M.Friedl (HEPHY Vienna): Belle II SVD Readout

  16. Introduction Front-End Junction Box FADC DAQ Summary M.Friedl (HEPHY Vienna): Belle II SVD Readout

  17. Junction Box: Mother Board • Junction box board with CERN DC/DC converters to be placed in SVD DOCK boxes • Converter boards now have a commercial chip, to be replaced by the rad-hard AMIS5 chip M.Friedl (HEPHY Vienna): Belle II SVD Readout

  18. DC/DC Converter: Noise Comparison • Same noise within measurement precision (few %) between conventional and DC/DC powering! Test hybrid (larger) Belle II design(smaller) M.Friedl (HEPHY Vienna): Belle II SVD Readout

  19. Junction Box: Draft Design • (Top lid not shown) • As in Belle 1 SVD: Located ~2m from front-end (outside acceptance) = radiation zone • Mostly aluminum, only bottom plate copper (to be cooled) M.Friedl (HEPHY Vienna): Belle II SVD Readout

  20. Introduction Front-End Junction Box FADC DAQ Summary M.Friedl (HEPHY Vienna): Belle II SVD Readout

  21. Readout Electronics: Scheme • No direct connection between power supplies and FADC • Bias currents are measured remotely by FADC M.Friedl (HEPHY Vienna): Belle II SVD Readout

  22. FADC Block Diagram • Analog & digital level translation between  bias and GND • Digitization, signal conditioning (FIR filter), data processing • Central FPGA is an AlteraStratix IV GX M.Friedl (HEPHY Vienna): Belle II SVD Readout

  23. FADC: Overall Concept • Similar to Belle 1 SVD FADC, but with twice higher density (48 APV25 inputs) and more powerful FPGA M.Friedl (HEPHY Vienna): Belle II SVD Readout

  24. FADC: Level Translation Daughter Boards • Analog board: existing design, but simplified • Digital board: completely new design based on digital isolator ICs (Analog Devices) • No floating LV power needed for either board! M.Friedl (HEPHY Vienna): Belle II SVD Readout

  25. FADC: Level Translation Tests APV25 Hybrid Ana+Digi daughter boardson adapter board APVDAQ Repeater • Both boards tested thoroughly, working perfectly fine  • Short (2m) and long (12m) cable to FADC • 100V between floating and GND sides • No damage with repeated instantaneous shorting of HV M.Friedl (HEPHY Vienna): Belle II SVD Readout

  26. Introduction Front-End Junction Box FADC DAQ Summary M.Friedl (HEPHY Vienna): Belle II SVD Readout

  27. Finesse Transmitter Board (FTB) • Sends FADC data through optical link to • COPPER • Pixel system (for online data reduction) • Firmware in development Markus Friedl (HEPHY Vienna): Status of SVD

  28. COPPER = Common Readout Platform • Standardized 9U VME crate with CPU and network interface • 4 slots for FINESSE daughter boards (ADC, TDC, …) according to subsystem needs • In case of SVD: Belle2Link (Optical receiver) M.Friedl (HEPHY Vienna): Belle II SVD Readout

  29. Introduction Front-End Junction Box FADC DAQ Summary M.Friedl (HEPHY Vienna): Belle II SVD Readout

  30. Overall Readout System Scheme • DAQ: PC Farm • COPPER: common readout platform • FADC system with optical link to COPPER • DOCK box with DC/DC • Front-End M.Friedl (HEPHY Vienna): Belle II SVD Readout

  31. Summary & Outlook • Belle I  Belle II • Needs completely new vertex detector (pixel + strips) • Readout Chain • Based on a 2007 design (for an earlier update option)  • “Origami” chip-on-sensor concept for front-end with APV25 • Junction box near front-end with rad-hard DC/DC converters • No noise penalty from switching power  • FADC with powerful FPGA for online signal processing • Level translation daughter boards – working fine  • DAQ link to common readout platform • Will report on performance at next TWEPP  M.Friedl (HEPHY Vienna): Belle II SVD Readout

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