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MICROPROCESSOR BASED SYSTEM DESIGN

MICROPROCESSOR BASED SYSTEM DESIGN. Lecture # 15 - 16. BY PROF. DR. B. S. CHOWDHRY. Five surgeons from big cities are discussing who makes the Best Patient to operate on. The first surgeon, from New York, says, 'I like to see accountants

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MICROPROCESSOR BASED SYSTEM DESIGN

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  1. MICROPROCESSOR BASED SYSTEM DESIGN Lecture # 15 - 16 BY PROF. DR. B. S. CHOWDHRY

  2. Five surgeons from big cities are discussing who makes the Best Patient to operate on • The first surgeon, from New York, says, 'I like to see accountants on my operating table because when you open them up, everything inside is numbered.' • The second, from Chicago, responds, 'Yeah, but you should try electricians! Everything inside them is color coded.' • The third surgeon, from Dallas, says, 'No, I really think librarians are the best, everything inside them is in alphabetical order.' • The fourth surgeon, from Los Angeles chimes in: 'You know, I like construction workers...Those guys always understand when you have a few parts left over.' • But the fifth surgeon, from Washington, DC shut them all up when he observed: 'You're all wrong. Politicians are the easiest to operate on. There's no guts, no heart, no balls, no brains, no spine, NO MEMORY..

  3. MEMORY INTERFACE • Whether simple or complex, every microprocessor based system has a MEMORY system. • The Intel family of microprocessors are no different from any other in this respect. • Two main types of memory: RAM & ROM. • ROM contains System Software & Permanent System Data. • RAM contains Temporary data & Applications Software.

  4. MEMORY PIN CONNECTIONS • Every memory device must have: • Address inputs • Data inputs & outputs • Some type of selection input • At least on control input to select Read/Write operation.

  5. ADDRESS CONNECTIONS: All memory devices have address inputs that select a memory location within the memory device.

  6. Most common memory devices have locations of:

  7. A 1K memory device has 10 address pins (A0 – A9). 4Kmemory device has 12 address connections, an 8Kdevice has 13, & so forth. • A device that contains 1M locations requires a 20-bit Addresses (A0 – A19). • A device that contains 16Mlocation requires a 24-bit addresses (A0 – A23). • A device that contains 4G location requires 32-bit address.

  8. READ MOSTLY MEMORY (RMM) • These are called FLASH MEMORY Devices. • The FLASH memory is often called an EEPROM, EAROM or a NOVRAM (Non Volatile RAM). • These devices are electrically erasable in the system, but require more time to erase than normal RAM. • The Flash Memory device is used to store setup information for systems such as Video Card in computer, replaced the ROM BIOS of the PC, and Password as well.

  9. Famous series of EPROM is 27 XXX: Each of these parts contains ADDRESS PINS, 8 Data Pins, one or more chip selection inputs (CE), and an output Enable Pin (OE). Access time varies from 100 ns to 450 ns.

  10. STATIC RAM DEVICE • Static RAM devices retain data for as long as DC power is applied. • Because no special action (except power) is required to retain stored data, these devices are called STATIC MEMORY. • They are also called VOLATILE MEMORY because they do not retain data without power.

  11. This device has 11 address inputs & 8 data input/output connections. • This device is representative of all SRAM devices. • Control pins are named slightly different than that of EPROM: • OE pin is labeled as G • CS pin is labeled as S • WE pin is labeled as W • Other manufacturer make this POPULAR SRAM under part No. 2016 & 6116. • Typical access time 120 ns. • Fast SRAM with access time as little as 10ns are also available (Cache Memory).

  12. DYNAMIC RAM (DRAM) MEMORY • The largest static RAM available today is a 128K x 8. • DRAM are available in much larger sizes upto 256MB x 1. • DRAM is essentially the same as SRAM, except that it retains data for only 2 or 4 ms on an integrated capacitor. • After 2 or 4 ms, the contents of the DRAM must be refreshed (rewritten) because the capacitors which store a logic 1 or logic 0, loose their charges. • Another disadvantage of DRAM memory is that it requires so many address pins that the manufacturer have multiplexed the address inputs.

  13. It contains only 8 address inputs where as it should contain 16 address lines to address 64 K locations. • The only way that 16 address bits can be forced into 8 address pins is in two 8bit increments. • This operation is performed by two special pins called column address Strobe (CAS) and Row address Strobe (RAS). • First A0- A7 are placed on the address pins and strobes into an internal row latch by (RAS) as the row address. • Next, the address bits A8-A15 are placed on same 8 address inputs (A0-A7) and strobed into an internal column latch by CAS as the column address.

  14. The CAS also performs the function of the chip selection input. • Typical access time 70 ns. • Larger DRAMS are available: • 1Mx1, 4Mx1, 16Mx1, 32Mx1, 64 Mx1, 128Mx1, 256Mx1, 512Mx1, 1GBx1 • DRAM memory is usually placed on SIMMs (Single In-line Memory Modules). • 30 pin SIMM is organized most often as 1Mx8 or 1Mx9 and 4Mx8 or 3Mx9 (the 9th bit the parity bit). • 72 pin SIMMS are often organized as 1Mx32 or 1Mx36 (with parity).

  15. HARDWARE ORGANIZATION OF THE MEMORY ADDRESS SPACE • From hardware point of view, the memory address spaces of the 8088 & 8086 based microcomputers are organized differently. • 8088’s memory subsystem is implemented as a single 1Mx8 memory bank. • These byte-wide storage locations are assigned to consecutive addresses over the range from 00000H through FFFFFH. • During memory operations, a 20-bit address is applied to the memory bank over single lines A0 through A19. • Address on address lines selects the storage location that is to be accessed. • Bytes of data are transferred between the 8088 and memory over the data bus lines D0 – D7.

  16. 8086 memory address space is implemented as two independent 512K-bytes banks: Low (EVEN) BANK & HIGH (ODD) BANK. • Data bytes are associated with an even addresses (00000H, 00002H, … so on) reside in low bank and those with odd addresses (00001H, 00003H, … so on) reside in high bank. • Address bits A1 – A19 select the storage locations that is to be accessed. Therefore THEY ARE APPLIED TO BOTH BANK’S IN PARALLEL (Refer figure).

  17. A0 and the Bank (Bus) High Enable (BHE) are used as bank select signals. • Logic 0 at A0 identifies an even-addressed byte of data and causes the low bank of memory to be enabled. • BHE equal to 0 enables the high bank of access of an odd-addressed byte of data. • Each of the memory bank provides half of the 8086’s 16-bit data bus. • Lower bank transfers bytes of data over data lines (D0 – D7), while data transfers for high bank use D8 – D15.

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