Hongshin Jun, Bill Eklow 9/15/2010 BTW10, Fort Collins, CO

1. PCC - Programmable Clock Control for Characterization and TestOn chip test clock margining and calibration Hongshin Jun, Bill Eklow 9/15/2010 BTW10, Fort Collins, CO

2. ClassicalScaling Industry Trend: Nominal Variation Variation Effects with Performance as Technologies Evolve With less margin & more variability & modeling becoming more difficult -- we need to be more thorough during debug, verification & testing to avoid margin-driven failures. Performance Technology generation

3. Problem Statement • Latest Semiconductor Technology • More Delay (Timing) Faults • Accumulation of marginal parts = board/system level failure • End result = NTFs • ASIC Failure Analysis Challenges • System/Board • Functional Test • Noisy Environment • Isolation is difficult • ATE • Structural Test • Different from Real Env. • More diagnostic capability (shmoo), but tests are not relevant

4. Problem Statement • Test Performance Characterization Needed • Margin Prediction • Debug (Chip in system) • Data Driven Debug (All About Outliers) • On Chip Clock Control (PCC) • Allows for clock margining at very granular intervals • Can be used in conjunction with current BIST tests • Can be used to help characterize “environmental” effects (power, crosstalk, ….) • Trend data can be used for outlier detection

5. On-chip Test Clock Generation • Programmable test clock generator (IP) • Clock waveform measurement (IP) • On-chip clock margining responsive to clock measurement (Integration) • For better failure analysis and quality of ASIC

6. Pulse Selection Method • Delayed clock generator, Pulse PSG, and MUX

7. Edge Selection Method • Resolution: one buffer delay in the technology

8. On-chip Timing Measurement Signal Input (SCLK) DMON SCLK EDGE Accumulation

9. IP Design TDR DMON TDR • IP Includes • Delay Chain, Delay Chain Monitor, and MUX tree • Design Requirements • Linear delay values in delay chain • Balance delay in MUX tree (both data and selection) • Minimize delay variations over PVT • No glitch

10. IP Design – Clock generation • Dcalmux128 • 90 nm technology • 128-tap delay chain • Support 125MHz or higher • 4711 um2 or 1072 gates • Resolution • 30ps in Best • 70ps in Worst

11. PCC integrated in Cisco Clock Stopper • Works with any ATPG/LBIST, JTAG Interface PLL 1x refClk Normal CS TDR TDR TDR TDR TDR DMON TDR TDR 2x Normal CS TDR TDR TDR TDR TDR TDR DMON TDR

12. Characterization

13. Characterization: Delay Buffers • Linear delay values in the delay chain • 30ps in BC ~ 90ps in Worst

14. LBIST Shmoo Correlation 7.656ns 5.904ns 5.173ns 7.750ns 5.750ns 5.0ns

15. AC Scan Clock Period Stretch • At-speed clock period stretch • The test might be done at slower frequency than at-speed • Need to measure the amount and compensate it • On-chip clock waveform measurement * Graph from “Calibrating clock stretch during AC scan testing”, ITC 2005, by Jeff Rearick, Agilent

16. Double capture fail at 2.46ns

17. Burst capture fail at 2.65ns

18. LBIST Shmoo 2.46 ns 2.65 ns 3.47ns (288MHz) -> 190ps Stretch -> 3.66ns (273MHz)

19. Clock Tree Calibration Mode • Generate test clock responsive to DMON PLL 1x refClk Normal CS TDR TDR TDR TDR TDR TDR DMON TDR 2x Normal CS TDR TDR TDR TDR TDR Same DMON as functional mode DMON TDR TDR

20. 65n, dcalmux64 Best +/- 30*n ps Typical +/- 60*n ps Worst +/- 98*n ps Jitter Insertion: Freq. Stress in EDVT Cs1_pcc_sysClk375 Jitter Jitter Jitter Jitter How much Jitter? Jitter 1.33n jt_rs[6:0] jt_fs[6:0]

21. Summary • On-chip Clock Margining and Calibration • Margin Characterization & Analysis over End-to-End • Shmoo LBIST / ATPG tests in board/system environment: • Shmoo LBIST for an ASIC while other components are running functionally on board. Can identify “environmental effects”. • Debug ASIC on board with specially generated ATPG (path-delay, bridging, small-delay) patterns on board, to isolate on chip margin defects. • CM can collect LBIST shmoo data without ATE. Supplier can potentially debug the failure without the part. Can possibly be used to identify outlier characteristics as well • PCC Jitter Insertion allows Frequency Stress in EDVT • Works with any functional pattern • Functional BIST

23. ASICs with PCC

24. Jitter Insertion: When to insert.. Jt_cnt[31:1] 0 1 start input: Jt_cnt starts when 1/2 is high jt_phase[0] jt_int[31:1] jt_phase_inc[0] Jt_cnt[0] 0 1 0 1 1x 1/2 1x 1/2 1x 1/2 1x 1x Stress 1/2 1/2 No stress Jt_int=5, Jt_phase=0 Jt_int=5, Jt_phase=1 Jt_cnt[31:1] 0 1 2 3 4 5 0 1 2 3 4 5 Jt_cnt[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1x 1/2 Jt_int=1, Jt_phase=0 Jt_int=1, Jt_phase=1 Jt_cnt[31:1] 0 1 0 1 0 1 0 1 0 1 0 1 Jt_cnt[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1x 1/2

25. Nile LBIST Noise Effect

26. References EDCS-406952: Programmable delay fault test clock generator EDCS-576749: AC scan clock calibration using PCC On-chip timing uncertainty measurements on IBM microprocessors, ITC, 2007 Calibrating clock stretch during AC Scan Testing, ITC, 2005