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USB IP Subsystem-USB 3.1 Device Controller

We offer a USB IP subsystem, FPGA boards, SERDES interface, USB 3.1 Device Controller, USB 3.2 Retimer, SRI's architecture, MCU CSR interface.

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USB IP Subsystem-USB 3.1 Device Controller

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  1. OPENFIVE

  2. USB IP Subsystem - USB 3.1 Device Controller • SiFive provides a complete portfolio of USB-certified controllers with host and device functionality. • They are integrated with our PHY partners in multiple foundries and nodes. FPGA boards are available for demo and prototype use. • We offer USB IP subsystem, FPGA boards, SERDES interface, USB 3.1 Device Controller, USB 3.2 Retimer, SRIS architecture, MCU CSR interface.

  3. USB 3.1 Device Controller Key Features • Compliant with USB 3.1 Gen 2 specification, USB 3.1 PIPE interface • Supports 32/64 data bus width • AXI, AHB bus standards • Supports 32/64/128 bit data bus • Supports all USB 3.1 power down modes • Supports Ccontrol, bulk, Iiochronous and interrupt transactions • Bulk endpoint support streaming • Device can be configurable up to 15 IN and 15 OUT functional endpoints • Configurable number of function endpoints • Dynamically configurable endpoint FIFO for optimum usage of memory • Synchronous SRAM interface for FIFO • Fully integrated DMA controller

  4. Download • USB 3.0 OTG datasheet - PDF • USB 3.1 Gen2 Device datasheet - PDF • USB 3.1 Retimer Product Brief - PDF

  5. Please do visit my website for in-depth information. Website: https://openfive.com/ USB IP Subsystem : https://openfive.com/usb-ip-subsystem/

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