Moore’s Law

1. Moore’s Law • Gordon Moore: co-founder of Intel. • Predicted that number of transistors per chip would grow exponentially (double every 18 months). • Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles.

2. Moore’s Law plot

3. The cost of fabrication • Current cost: $2-3 billion. • Typical fab line occupies about 1 city block, employs a few hundred people. • New fabrication processes require 6-8 month turnaround. • Most profitable period is first 18 months-2 years.

4. Cost factors in ICs • For large-volume ICs: • packaging is largest cost; • testing is second-largest cost. • For low-volume ICs, design costs may swamp all manufacturing costs. • $10 million-$20 million.

5. Mask cost vs. line width

6. Field-programmable gate arrays • FPGAs are programmable logic devices: • Logic elements + interconnect. • Provide multi-level logic. LE Interconnect network LE LE LE LE LE

7. FPGAs and VLSI • FPGAs are standard parts: • Pre-manufactured. • Don’t worry (much) about physical design. • Custom silicon: • Tailored to your application. • Generally lower power consumption.

8. Standard parts vs. custom • Do you build your system with an FPGA or with custom silicon? • FPGAs have shorter design cycle. • FPGAs have no manufacturing delay. • FPGAs reduce inventory. • FPGAs are slower, larger, more power-hungry.

9. Challenges in system design • Multiple levels of abstraction: logic to CPUs. • Multiple and conflicting constraints: low cost and high performance are often at odds. • Short design time: Late products are often irrelevant.

10. FPGA-based system design The system design process • May be part of larger product design. • Major levels of abstraction: • specification; • architecture; • logic design; • circuit design; • layout.

11. Elements of an FPGA fabric • Logic. • Interconnect. • I/O pins. … … IOB IOB IOB LE LE LE interconnect LE LE LE LE LE LE

12. Terminology • Configuration: bits that determine logic function + interconnect. • CLB: combinational logic block = logic element (LE). • LUT: Lookup table = SRAM used for truth table. • I/O block (IOB): I/O pin + associated logic and electronics.

13. Logic element • Programmable: • Input connections. • Internal function. • Coarser-grained than logic gates. • Typically 4 inputs. • Generally includes register. • May provide specialized logic. • Adder carry chain.

14. 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 1 Example logic element • Lookup table: memory a out b

15. Logic synthesis • How do we break the function into logic elements? • How do we implement an operation within a logic element?

16. Placement • Where do we put each piece of logic in the array of logic elements? … LE LE LE LE LE LE LE LE LE

17. Programmable wiring • Organized into channels. • Many wires per channel. • Connections between wires made at programmable interconnection points. • Must choose: • Channels from source to destination. • Wires within the channels.

18. Programmable interconnection point D Q

19. Programmable wiring paths

20. Choosing a path LE LE

21. Routing problems • Global routing: • Which combination of channels? • Local routing: • Which wire in each channel? • Routing metrics: • Net length. • Delay.

22. Segmented wiring Length 1 Length 2

23. Offset segments

24. I/O • Fundamental selection: input, output, three-state? • Additional features: • Register. • Voltage levels. • Slew rate.

25. Programming technologies • SRAM. • Can be programmed many times. • Must be programmed at power-up. • Antifuse. • Programmed once. • Flash. • Similar to SRAM but using flash memory.

26. Configuration • Must set control bits for: • LE. • Interconnect. • I/O blocks. • Usually configured off-line. • Separate burn-in step (antifuse). • At power-up (SRAM).

27. FPGA configuration: Bits stay at the device they program. A configuration bit controls a switch or a logic bit. CPU programming: Instructions are fetched from a memory. Instructions select complex operations. Configuration vs. programming memory CPU add r1, r2 IR add r1, r2

28. Reconfiguration • Some FPGAs are designed for fast configuration. • A few clock cycles, not thousands of clock cycles. • Allows hardware to be changed on-the-fly.

29. FPGA fabric architecture questions • Given limited area budget: • How many logic elements? • How much interconnect? • How many I/O blocks?

30. Logic element questions • How many inputs? • How many functions? • All functions of n inputs or eliminate some combinations? • What inputs go to what pieces of the function? • Any specialized logic? • Adder, etc. • What register features?

31. Interconnect questions • How many wires in each channel? • Uniform distribution of wiring? • How should wires be segmented? • How rich is interconnect between channels? • How long is the average wire? • How much buffering do we add to wires?

32. I/O block questions • How many pins? • Maximum number of pins determined by package type. • Are pins programmed individually or in groups? • Can all pins perform all functions? • How many logic families do we support?