Co-optimization of Memory BIST Grouping, Test Scheduling, and Logic Placement

1. Co-optimization of Memory BIST Grouping, Test Scheduling, and Logic Placement Andrew B. Kahng and Ilgweon Kang VLSI CAD LABORATORY, UC San Diego Design, Automation & Test in Europe March 26th, 2014

2. Outline • Motivation and Contributions • Related Works • ILP Formulation • Heuristic Flow • Experimental Results • Conclusions and Future Work

3. Motivation • Memory built-in self-test (MBIST) • Essential DFT technique in modern SOCs • MBIST design impacts chip resources and quality of test solution • Physical optimizations of MBIST logic: not well-studied MEM MEM MEM MEM BIST MEM BIST MEM MEM MEM MEM MEM MEM BIST MEM BIST MEM MEM MEM MEM BIST MEM MEM TAP Memory BIST Architecture

4. Challenges and Contributions • Challenge: Multiple optimization criteria • Minimize test time • Minimize number of BIST controllers • Minimize wirelength between BIST logic and memories • Our work: Three-stage heuristic • Memory partitioning : FM in a weighted hypergraph model • Test scheduling : Integer Linear Program (ILP) formulation • MBIST logic placement : min-weight maximum matching

5. Outline • Motivation and Contributions • Related Works • ILP Formulation • Heuristic Flow • Experimental Results • Conclusions and Future Work

6. Related Works • Test scheduling • Reduction of test time is a fundamental goal in DFT • Typical: scheduling as rectangle packing • Also typical: scheduling as ILP • Design optimizations for memory BIST controllers • Most works focus on architectural and testing aspects • Chien et al. [2009] propose a memory BIST design optimization • ILP for clustering of memories to controllers • Studies physical design aspects • Various simplifications: all of a cluster is tested in parallel, no two clusters tested simultaneously, …

7. Outline • Motivation and Contributions • Related Works • ILP Formulation • Heuristic Flow • Experimental Results • Conclusions and Future Work

8. ILP Formulation • Objective: Minimize test end time • Subject to: Upper bound on test power • Logical constraints capture parallel and serial testing scenarios Test power limit Test power limit power power MBIST1 MEM1 MEM3 MEM2 MEM4 MEM1 MBIST1 MEM8 MEM5 MEM2 MBIST2 MEM5 MEM7 Reduced test time MEM6 MEM3 MBIST2 MEM6 MEM9 MEM9 MEM4 MEM7 MEM8 time time Test time with one solution Improved test time is possible

9. Outline • Motivation and Contributions • Related Works • ILP Formulation • Heuristic Flow • Experimental Results • Conclusions and Future Work

10. Overall Flow Input: Memories, Constraints Memory Partitioning with Hypergraph (MLPart [1], FM-style) (2) Test Scheduling with ILP formulation (CPLEX [2], logical constraints) (3) Placement of BIST Logic for each Partition ([3], Min-Weight Max-Cardinality Matching) Output: Memory BIST Groups, Test Schedules, BIST Logic Placements [1] MLPart. http://vlsicad.ucsd.edu/GSRC/bookshelf/Slots/Partitioning/MLPart [2] IBM ILOG CPLEX Optimizer. http://www.ilog.com/products/cplex [3] Hungarian algorithm source code. http://www.informatik.uni-freiburg.de/~stachnis/index.html

11. Memory Partitioning • Divide memories into k partitions using MLPart • MLPart: Min-cut hypergraph partitioner based on multilevel FM • k = number of BIST controllers • Hypergraph: vertices = memories; hyperedge weights reflect test time implications of grouping • Reduced test time if memories with same shape and depth in same group MEM MEM MEM MEM MEM MEM • Hyperedges: The same shape, depth and test power, respectively • Edges: Distances < D1, < avg(D1, D2) and< D2, respectively (where D1< D2) MEM MEM Example Hypergraph

12. Test Scheduling • Solve ILP formulation • Minimize test time, subject to power constraint • ILP solver: CPLEX Optimizer 12.5.1 • Additional partition (BIST controller) for better test time • Obtain alternative test scheduling solution with extra BIST controller • {1 BIST controller, 2 BIST controllers} per each partition MEM MEM MEM MEM MEM MEM MEM MEM BIST1 MEM MEM MEM MEM BIST1 MEM MEM MEM MEM MEM MEM BIST2 MEM MEM MEM MEM Est. Test Time 1000 Est. Test Time 900 Solution with one BIST controller Solution with two BIST controllers

13. Memory BIST Logic Placement • To minimize wirelength between each BIST and memories • Min-weight maximum-cardinality matching in a bipartite graph • Apply Hungarian algorithm • Cost: Diameter from a grid to all memories in a group Forbidden grids (intersection with memories) MEM MEM MEM MEM MEM MEM MEM MEM BIST placement solution MEM Possible grids for BIST logic placement Memories in the same BIST group

14. Outline • Motivation and Contributions • Related Works • ILP Formulation • Heuristic Flow • Experimental Results • Conclusions and Future Work

15. Experimental Setup • Develop MBIST-solver to implement our heuristics • C++ / g++ 4.8.0 • User options include min/max # partitions, min/max # memories in a partition, max diameter, power constraint, weight parameters, … • MLPart: Memory partitioner • CPLEX 12.5.1: ILP solver • Testcases: six industrial testcases (from industry partners) TC = testcase M = #memories P = #partitions DMAX = maximum diameter w/o BIST [μm]

16. Experimental Results Our solutions • Reduce test time by up to 11.57% (Testcase3) • Reduce number of BIST controllers by up to 41.6% (Testcase6) • Reduce maximum diameter by up to 31.7% (Testcase 6) Large Maximum Diameter Smaller Maximum Diameter memories BIST controller • Industrial solution (TC1) • Test time = 1067 • # BISTs = 13 • Maximum Diameter = 3900μm • Our solution (TC1) • Test time = 969 • # BISTs = 12 • Maximum Diameter = 2100μm

17. Outline • Motivation and Contributions • Related Works • ILP Formulation • Heuristic Flow • Experimental Results • Conclusions and Future Work

18. Conclusions and Future Work • Three-step heuristic methodology • Co-optimization of (1) Memory BIST grouping, (2) test scheduling, and (3) memory BIST logic placement • Objective: minimize test time for a given #BIST controllers • Handle various serial / parallel testing options in ILP • Minimize diameter of BIST groups  less-critical timing, less need for LVT instances in BIST implementation, etc. • Future work • Integrate these optimizations into ‘production’ PD flow • Improve hypergraph weighting, scalability of ILP • Improve congestion- and timing-awareness of BIST placement

19. Thank You!