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Memory Access Scheduling

Memory Access Scheduling. Taidi Chen Fall 2006. Background. Memory bandwidth bottleneck 3-D structure of banks, rows and columns characteristic of DRAM chips bank precharge  row activation  column access

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Memory Access Scheduling

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  1. Memory Access Scheduling Taidi Chen Fall 2006

  2. Background • Memory bandwidth bottleneck • 3-D structure of banks, rows and columns characteristic of DRAM chips • bank precharge  row activation  column access • Memory access scheduling reorder memory operations to exploit the non-uniform access time of the DRAM

  3. Goal

  4. DRAM architecture • 3-D architecture of DRAM • Timing and resource constraint • bank state diagram • Resource utilization • Shared address

  5. Bank state diagram • Idle state • Precharge and ready for a row access • Switch to active state when a row activate operation is issued • Active state • the content of the selected row are held in the bank’s row buffer • Column access • Switch to idle state when a precharge operation is issued

  6. Resource Utilization • Both precharge and row operation occupied the bank resource • Data return from read after three cycles • Data to write must be transfer to DRAM at the time of issue

  7. Memory Access scheduler

  8. Scheduling policies (I) • In-order • Operation will only be performed if it is required by the oldest pending reference • Priority • Operation required by the highest priority ready references are performed • Ordered – older references are given higher priority • Age-threshold – references older than some threshold age gain increased priority • Load-over-store – load references are given higher priority

  9. Scheduling policies (II) • Open • A bank is only precharged if there are pending reference to other rows in the bank and there are no pending reference to the active row • Take advantage of row locality • Closed • A bank is precharged as soon as there are no more pending references to the active row

  10. Scheduling policies (III) • Most pending • The row or column access to the row with the most pending references is selected • Active row has highest column to row access ratio • Fewest pending • Selects the column access to the row targeted by the fewest pending references • Minimize the time that rows with little demand remain active

  11. Conservative Scheduling • Also known as First-ready scheduling • Use the ordered priority scheme • Allow access to different banks at the same time • Improve up to 79%

  12. Aggressive scheduling • Take advantage of open/closed policies • Improve up to 106-144%

  13. Aggressive scheduling (106-144%) (27-30%) (85-93%)

  14. Intel P965 chipset Source: Intel.com

  15. Intel P965 chipset source: Intel.com

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