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Advanced Encryption Standard For Smart Card Security

This research paper explores the implementation of the AES algorithm for smart card security using Verilog HDL. It covers encryption, decryption, key expansion, and system architecture. The study includes goals, work plan, and schedule for hardware realization.

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Advanced Encryption Standard For Smart Card Security

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  1. Advanced Encryption StandardFor Smart Card Security Aiyappan Natarajan David Jasinski Kesava R.Talupuru Lilian Atieno Advisor: Prof. Wayne Burleson

  2. Outline • Introduction • System Architecture • Encryption • Decryption • Goals • Work Plan & Schedule

  3. Introduction • Security in Smart Cards - Cryptography • Applications • Identification Cards • Credit Cards • Algorithms Used • Rijndael • DES(Data Encryption Standard) • RSA(Ronald, Samir and Adleman)

  4. Overall Block Diagram ISA Reset clk Processor FSM Req I/P I/P FSM Ready I/P Reset clk clk I/P Key 256 Encrypt Key Sched 16 Sub key clk 256 O/P FSM Reset 16 O/P Ready O/P Request O/P

  5. Encryption • Sub Bytes( ) Transformation • Shift Rows( ) Transformation • Mix Columns( ) Transformation • Add Round Key( ) Transformation • Key Expansion

  6. Encryption Algorithm Flow Raw Data Sub Key Key Add Substitution Shift Row Mix Column Key Add Sub Key Repeat (Round-1) times ED Key Add Shift Row Substitution Sub Key

  7. Decryption • Inverse Shift Rows( )Transformation • Inverse Sub Bytes( )Transformation • Add Round Key( )Transformation • Inverse Mix Columns( )Transformation

  8. Goals • Hardware Implementation of the Rijndael algorithm using Verilog HDL • Functional Verification of the code with the help of the available test vectors • Synthesis of Verilog Code • Verification of the functionality of the synthesized structure • Speed and Area Estimations

  9. Work Plan & Schedule • Kesava & Lilian – Encryption & Decryption Core • David – Key Expansion Module • Aiyappan – I/P & O/P Controller, Processor FSM • Behavioral Model – March 10th • RTL model – April 20th • Synthesis – April 30th • Verification – May 15th

  10. References • Draft of AES - Federal Information Processing Standards Publication, Washington D.C. • Kuo, Henry and Ingrid Verbauwhede- Architectural Optimization for a 1.82Gbits/sec VLSI implementation of the AES Rijndael Algorithm • Rankl and W.Effing- Smart Card Handbook, Second Edition, Chichester, England, John Wiley & Sons Ltd.,2000

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