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Front-end electronics developments for TESLA

Front-end electronics developments for TESLA. R. CHICHE, C. de LA TAILLE, G. MARTIN-CHASSARD LAL Orsay G. BOHNER J. LECOQ LPC Clermont http::/www.lal.in2p3.fr/technique/se/flc. Front-end test chip for HPD readout (opera). Complete front-end chip, 16 inputs, 1 trigger + 1 multiplexed output

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Front-end electronics developments for TESLA

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  1. Front-end electronics developments for TESLA R. CHICHE, C. de LA TAILLE, G. MARTIN-CHASSARD LAL Orsay G. BOHNER J. LECOQ LPC Clermont http::/www.lal.in2p3.fr/technique/se/flc

  2. Front-end test chip for HPD readout (opera) • Complete front-end chip, 16 inputs, 1 trigger + 1 multiplexed output • low noise charge preamplifier (Cf = 0.25 pF) • Fast shaper (75ns) for auto-trigger • Slow shaper (500 ns) for accurate charge measurement (minimum noise) • On chip track and hold and output multiplexer CdLT Calice collaboration meeting

  3. Measurement results (I) • Preamplifier • Test channel with preamp output accessible, followed by variable shaper • Preamplifier gain : 1.8 mV/p.e. (1 p.e. = 3000 e-) • Rise time : tr = 90 ns • Good agreement with simulation, except for noise Preamp output Qin=10 p.e. CdLT Calice collaboration meeting

  4. HPD preamp Noise measurements • HPD preamp (2000/0.8 PMOS) • ID = 0.5 mA, gm = 7.1 mA/V, en = 1.7 nV/√Hz, Ca = 8 pF, • Significant gate resistance (RG ~ 80 W). and substrate resistance noise contribution • Capacitance breakdown : • PMOS : 2.5 pF • input pads : 0.8 pF • Cf+Cinj : 0.5 pF • package : 1 pF • PCB : 2.4 pF CdLT Calice collaboration meeting

  5. 10000/0.8 PMOS Noise improvement • ATLAS CALIB 10 000/0.8 AMS PMOS transistor : • ID = 0.5 mA, gm = 8 mA/V, en = 1.0 nV/√Hz, Ca = 21 pF • Minimum gate resistance (RG ~ 2 W) and substrate resistance noise contribution CdLT Calice collaboration meeting

  6. Noise improvement • New layout for ~50% noise improvement • Size : 2000/0.8 similar transconductance (7 mA/V) with smaller capacitance (8 pF) • Different geometry to minimize gate resistance (RG : 80 → 2 W). • Bias substrate positively (VBS = +2V) to mimimize substrate noise contribution • gmb 1.8 mA/V -> 0.7 mA/V • Target : en = 1.0 nV/√Hz, Ca = 8 pF at ID = 0.5 mA ENC = 200 + 14 e-/pF @ tp = 150 ns CdLT Calice collaboration meeting

  7. Preamp design • Charge preamp : Cf = 5 pF • Input PMOS : • W/L = 2000/0.8 μm • ID = 500 μA • Grounded source • Nwell biased at +2V • Unfolded cascode CdLT Calice collaboration meeting

  8. Preamp design • Multiplied feedback resistance • Rf = 1000*100 k = 100 MΩ • Polarisation with Ig =1 nA • Associated noise : in = 60 fA/√Hz • Good linearity • Large dynamic range • 4 V output swing with 5.5 V power supply • !% non linerarity • BiCMOS AMS 0.8 um CdLT Calice collaboration meeting

  9. Preamp simulation results • Open loop gain and stability CdLT Calice collaboration meeting

  10. Preamp simulation results • Linearity CdLT Calice collaboration meeting

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