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Computer Organization. 4. The Von Neumann architecture. Stored Program Computers and Electronic Devices. Pattern. Jacquard Loom. Variable Program. Stored Program Device. Fixed Electronic Device. Assembly Language. ; Code for a = b + c load R3,b load R4,c
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ComputerOrganization 4 Operating Systems: A Modern Perspective, Chapter 4
The Von Neumann architecture Operating Systems: A Modern Perspective, Chapter 4
Stored Program Computers and Electronic Devices Pattern Jacquard Loom Variable Program Stored Program Device Fixed Electronic Device Operating Systems: A Modern Perspective, Chapter 4
Assembly Language ; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a ; Code for d = a - 100 load R4,=100 subtract R3,R4 store R3,d Program Specification Source int a, b, c, d; . . . a = b + c; d = a - 100; Operating Systems: A Modern Perspective, Chapter 4
Machine Language 10111001001100…1 10111001010000…0 10100111001100…0 10111010001100…1 10111001010000…0 10100110001100…0 10111001101100…1 Machine Language Assembly Language ; Code for a = b + c load R3,b load R4,c add R3,R4 store R3,a ; Code for d = a - 100 load R4,=100 subtract R3,R4 store R3,d Operating Systems: A Modern Perspective, Chapter 4
The von Neumann Architecture Central Processing Unit (CPU) Arithmetical Logical Unit (ALU) Control Unit (CU) Address Bus Data Bus Device Primary Memory Unit (Executable Memory) Operating Systems: A Modern Perspective, Chapter 4
The ALU load R3,b load R4,c add R3,R4 store R3,a Right Operand Left Operand R1 R2 . . . Rn Functional Unit Status Registers Result To/from Primary Memory Operating Systems: A Modern Perspective, Chapter 4
load R3,b load R4,c add R3,R4 store R3,a Fetch Unit 10111001001100…1 10111001010000…0 10100111001100…0 10111010001100…1 3050 PC Decode Unit IR load R4, c Execute Unit Control Unit Control Unit 3046 3050 3054 3058 Primary Memory Operating Systems: A Modern Perspective, Chapter 4
Control Unit Operation • Fetch phase: Instruction retrieved from memory • Execute phase: ALU op, memory data reference, I/O, etc. PC = <machine start address>; IR = memory[PC]; haltFlag = CLEAR; while(haltFlag not SET) { execute(IR); PC = PC + sizeof(INSTRUCT); IR = memory[PC]; // fetch phase }; Operating Systems: A Modern Perspective, Chapter 4
1234 98765 read 1. Load MAR with address 2. Load Command with “read” 3. Data will then appear in the MDR Primary Memory Unit 0 MAR 1 2 MDR Command 1234 98765 Read Op: n-1 Operating Systems: A Modern Perspective, Chapter 4
A Pipelined Function Unit Operand 1 Function Unit Result Operand 2 (a) Monolithic Unit Operand 1 Result Operand 2 (b) Pipelined Unit Operating Systems: A Modern Perspective, Chapter 4
A SIMD Machine ALU Control Unit (a) Conventional Architecture ALU Control Unit ALU ALU … ALU (b) SIMD Architecture Operating Systems: A Modern Perspective, Chapter 4
I/O Devices Operating Systems: A Modern Perspective, Chapter 4
Device manager • Program to manage device controller • Supervisor mode software Abstract I/O Machine The Device-Controller-Software Relationship Application Program Software in the CPU Device Controller Device Operating Systems: A Modern Perspective, Chapter 4
busy done 0 0 idle 0 1 finished 1 0 working 1 1 (undefined) Device Controller Interface . . . busy done Error code . . . Command Status Data 0 Data 1 Logic Data n-1 Operating Systems: A Modern Perspective, Chapter 4
Performing a Write Operation while(deviceNo.busy || deviceNo.done) <waiting>; deviceNo.data[0] = <value to write> deviceNo.command = WRITE; while(deviceNo.busy) <waiting>; deviceNo.done = TRUE; • Devices much slower than CPU • CPU waits while device operates • Would like to multiplex CPU to a different process while I/O is in process • It is called a spin-lock Operating Systems: A Modern Perspective, Chapter 4
Direct Memory Access Primary Memory Primary Memory CPU CPU Controller Controller Device Device Operating Systems: A Modern Perspective, Chapter 4
Addressing Devices Primary Memory Primary Memory Memory Addresses Device 0 Device 0 Memory Addresses Device 1 Device 1 Device Addresses Device n-1 Device n-1 Operating Systems: A Modern Perspective, Chapter 4
Interrupts Operating Systems: A Modern Perspective, Chapter 4
Detecting an Interrupt CPU InterruptRequest flag Device Device Device Operating Systems: A Modern Perspective, Chapter 4
memory[1] contains the address of the interrupt handler Control Unit with Interrupt (Hardware) while(haltFlag not SET) { IR = memory[PC]; execute(IR); PC = PC + 1; if(InterruptRequest) { memory[0] = PC; PC = memory[1] }; Operating Systems: A Modern Perspective, Chapter 4
Interrupt Handler (Software) interruptHandler() { saveProcessorState(); for(i=0; i<NumberOfDevices; i++) if(device[i].done) goto deviceHandler(i); /* something wrong if we get to here … */ deviceHandler(int i) { finishOperation(); returnToScheduler(); } Operating Systems: A Modern Perspective, Chapter 4
Disabling Interrupts if(InterruptRequest && InterruptEnabled) { /* Interrupt current process */ disableInterrupts(); memory[0] = PC; PC = memory[1]; } Operating Systems: A Modern Perspective, Chapter 4
… … … Ready Processes Ready Processes Ready Processes CPU CPU Device Device I/O Operation Uses CPU CPU-I/O Overlap CPU Device Operating Systems: A Modern Perspective, Chapter 4
Software interrupts(traps, system calls) Operating Systems: A Modern Perspective, Chapter 4
The trap Instruction (Hardware) executeTrap(argument) { setMode(supervisor); switch(argument) { case 1: PC = memory[1001]; // Trap handler 1 case 2: PC = memory[1002]; // Trap handler 2 . . . case n: PC = memory[1000+n];// Trap handler n }; • The trap instruction dispatches a trap handler routine atomically • Trap handler performs desired processing • “A trap is a software interrupt” Operating Systems: A Modern Perspective, Chapter 4
Branch Table 1 2 3 The Trap Instruction Operation Mode S trap Trusted Code User Supervisor Operating Systems: A Modern Perspective, Chapter 4
