MAPS readout Systems Christoph Schrader

MAPS readout SystemsChristoph Schrader Dresden -26.09.2007

Micro- Vertex DetectorMAPS (“Monolithic Area Pixel Sensors”) • Micro- Vertex Detector: • consists of two MAPS detector stations • ~ 20µs integration time • ~ 20µm pixel pitch •  20 Gb/cm2 raw data Fig.1: Sketch of the proposed CBM experiment

Vertex Demonstrator • Our MAPS-Chip (Mimosa-17): • consists of four matrices with parallel readout • 256 x 256 pixel/matrix • pixel by pixel readout • 1 ms readout speed/frame in 12 seconds  1 Gb Fig.2:Example for MAPS-chip with 4 matrices

TRBv2 and the add-on concept • TRBv2: • Etrax-FS-Processor • Ethernet-connectivity • an optical link with 2 Gbit/s • programmable logic (Vertex 4) Fig.3:The general-propose trigger and readout board (TRBv2) Fig.4:The MDC-add-on mounted on the TRBv2 – back side

Duties and responsibilities of the TRBv2 for the MAPS add-on • High data-rate digital interface connector (15Gbit/s) • FPGA configuration • High data transfer with optical link (2Gbit/s) • Application process interface (API) • Power supply +5V,10A • Clock distribution

System configuration of MAPS readout serves as support for the various versions of MAPS devices adapts/converts the signals control and collect measurement data Fig.5:A block diagram of system configuration for MAPS readout

Add-on board design AUXILIARY BOARD ADD-ON BOARD Fig.6:Diagram of the add-on components TRBv2

Data processing • Correlated double sampling • Data compression • Threshold

Pipelining as data processing Fig.7: Data processing way

Correlated double sampling by Self-Bias-Pixel Fig.8: The behaviour of SB-pixels is observed by frames. The constant current leakage in the capacitor is compensate through a diode. After hit the diode re-fill the capacitor ADC units 1900 fx:px threshold hit fx-1:px readout cycle ∆ ADC (fx:px - fx-1:px) Fig.9: Equivalent circuit diagram of SB-Pixel threshold Fig.10: AfterCDS clear hit identification is possible (fx-1:px - fx-2:px) acquisition cycle

Correlated double samplingand data compression Data compression • Correlated double sampling: • for noise reduction • difference between the • actual frame and the • frame before Fig.11: Different between the pixel by FIFO and SDRAM

Threshold The hit and the 8 neighbour pixel are important Result: not the complete matrix is readout, only the hit with the neighbour pixel Fig.12: Data selection with threshold

Project status • Board design (schematics) • Layout is advanced • Test the board hardware • Data processing concept • Data processing code (simulation)

THANK YOU

Add-on board design Fig.11: Add-on board

Simulation of Self-Bias-Pixel readout

Correlated double samplingby 3T-Pixel fx:px ADC units hit Fig.8: Equivalent circuit diagram fx-1:px readouto cycle Fig.9: The behaviour of 3T-pixels is observed by frames. The constant wastage is produced from the current leakage in the capacitor. (fx:px - fx-1:px) Fig.10: Past baseline the leakage current is cut out ∆ ADC (fx-1:px - fx-2:px) cycle

MAPS readout Systems Christoph Schrader