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A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System

A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System. Reference: Chiou-Kou Tung, “A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System,” Design and Diagnostics of Electronic Circuits and Systems (DDECS) , Poland, pp. 1-4, April 11-13, 2007. Student: Chien-Nan Lin.

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A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System

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  1. A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System Reference: Chiou-Kou Tung, “A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System,” Design and Diagnostics of Electronic Circuits and Systems (DDECS), Poland, pp. 1-4, April 11-13, 2007 Student: Chien-Nan Lin

  2. Outline • Introduction • Review • Proposed Method of Novel Full Adder Design • Conclusion

  3. Introduction In this paper, a low-powerhigh-speed CMOS full adder core is proposed. The five full adders will be compared with the new proposed full adder. There are two major methodologies to improve adder’s performance.

  4. Outline • Introduction • Review • Proposed Method of Novel Full Adder Design • Conclusion

  5. Review (1/5) Section review, which reviews the previous outstanding full adder designs. These five different types of adders are: • Conventional CMOS full adder • Transmission Function full adder • PTL-based full adder • HPSC full adder • Low-Energy Hybrid full adder

  6. Review (2/5) ex. Ci=0,A=B=1, S= ,C0= . ╳ ╳ ╳ ╳ ╳ ╳ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ ‘1’ ‘1’ 0 1 ╳ ‘1’ ‘1’ ╳ ‘1’ ‘0’ ‘0’ ‘0’ Defect: This configuration consumes smaller power, but its drawback comes from slower speed. ‘0’ ╳ ‘1’ ╳ ‘0’ ‘0’ ‘1’ ‘1’ ╳ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ ‘1’ ‘1’ Fig. 1. Conventional CMOS full adder

  7. Review (3/5) ex. Ci=0,A=B=1, S= ,C0= . ‘0’ 0 1 ‘0’ ‘1’ ╳ ‘0’ ‘0’ ‘1’ ‘1’ Defect: Its disadvantage is slow speed and high power consumption. ‘0’ ‘1’ ╳ ‘0’ ‘1’ ‘1’ ‘0’ ‘0’ ‘1’ Fig. 2. Transmission Function full adder

  8. Review (4/5) ex. Ci=0,A=B=1, S= ,C0= . ‘0’ 0 1 ‘1’ ‘0’ ╳ ‘0’ Defect: The whole full adder is slower down and consumes more power. ‘1’ ╳ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ Fig. 3. PTL-based full adder

  9. Review (5/5) Fig. 4. HPSC full adder (HPSC) Fig. 5. Low-Energy Hybrid full adder (LEHPSC) Defect: Two complementary transistor form the feedback loop to overcome the weak signals caused by pass transistor. The pass-logic module eliminate the whole propagation speed of the adder.

  10. Outline • Introduction • Review • Proposed Method of Novel Full Adder Design • Conclusion

  11. Novel Full Adder Design A. New Hybrid Full Adder (Conceptual diagram of the new full adder) (Proposed full adder core) Module 1 implement three-input XOR function to explain in B. Module 2 implement the function to explain in C. S = (A⊕B) ⊕Ci C0 = AB+(A+B)Ci

  12. Novel Full Adder Design B. Three-input XOR Circuit (a) Previous 3-XOR (b) New 3-XOR Although it is merely simple modification, the power consumption and speed are greatly improved. Normalized result Pd: Power dissipation Td: Time delay Power-delay product: Pd ╳ Td

  13. Novel Full Adder Design C. Carry-Out Module The PMOS tree mirrors to NMOS tree to simplify the chip layout consideration. The circuit is adopted as module 2 of the new full adder.

  14. Outline • Introduction • Review • Proposed Method of Novel Full Adder Design • Conclusion

  15. Conclusion A novel hybrid low-power full adder core with output driving capability had been presented in the paper. The compared results show that the performance of the proposed design is superior to other reference designs.

  16. Thanks

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