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Decoupling Capacitors Requirements

Decoupling Capacitors Requirements.

cynthiarichardson
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Decoupling Capacitors Requirements

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  1. Decoupling Capacitors Requirements Intel - Microprocessor power levels in the past have increased exponentially, which has led to increased complexity and cost of both power delivery and power removal. In particular, it has led to a need to exponentially lower the impedance of decoupling capacitors (lower inductance and resistance and higher capacitance).

  2. Decoupling Capacitors Requirements Powering high-slew-rate transient loads (such as LSI - microprocessors) require high frequency decoupling and typically uses parallel connection bank of capacitors (usually MLCCs, and low ESL Polymer Electrolytic caps) to provide low impedance up to several hundred MHz

  3. Decoupling Capacitors Requirements Capacitors reach their minimum impedance (Z = ESR) at their resonant frequency (Fos), which is determined by the capacitance value and the ESL of the capacitor. Fos- Resonant Freq (500KHz)

  4. Decoupling Capacitors Requirements The 'mounted inductance'(PCB) and ESL of a capacitor both contribute to the total inductance loop that current must flow within. The larger the loop, the more the inductance, and the slower the response. Reduction in total inductance is achieved by reducing the size of the current loop. The figure below shows a comparative study of various pad layout designs. Low Inductance Pad Layout PCB pad layout design & Inductance (nH - nanoHenry)

  5. Decoupling Capacitors Requirements Ideal capacitor An ideal capacitor can transfer all its stored energy to a load instantly. A real capacitor has parasitic inductance (ESL) that prevent instantaneous transfer of a capacitor’s stored energy. The ESL of a capacitor determines the speed of energy transfer from the capacitor to the load. Real world capacitor • Insulation Resistance ‘IR’ • DC leakage current • Energy loss • ESL • ESL impacts the speed of the capacitor response in transferring energy to the load • ESR • Limits current rating • Impacts ripple voltage • Energy loss

  6. Decoupling Capacitors Requirements • Reverse Geometry Low ESL Ceramic Chip Capacitors – MLCCs • Reduces ESL up to 60%! • Decoupling and noise suppression in high-speed circuits • Improved response time in power circuits • Reduce the number of decoupling components used • Reduce PCB size - costs and component placement costs! • 0204, 0306, 0508, 0612 case sizes • TCC: (Operating Temp) X7R (-55C to +125C) & X5R (-55C to +85C) • Capacitance Range 0.01uF (10nF) to 1.0uF • Rated Voltage Range: 6.3V to 50V Eight Low ESL MLCCs used In microprocessor decoupling Reverse geometry low ESL (Equivalent Series ‘L’ Inductance) MLCCs are ideal for use as high speed decoupling capacitors, mounted in close proximity or adjacent to microprocessorsLow inductance (low ESL) surface mount ceramic capacitors are connected directly to the power supply pins of the IC. Short traces or vias are required for this connection to minimize additional series inductance (ESL).

  7. Decoupling Capacitors Requirements Equivalent Series Inductance (L) NMC-R Series Performance Advantage

  8. Decoupling Capacitors Requirements Equivalent Series Inductance (L) ESL ≤ 0.20nH NMC-R Series Performance Advantage Increased Fos

  9. Decoupling Capacitors Requirements Top view of component • Low ESL Solid Polymer Aluminum Electrolytic Capacitors • 3-Terminal construction reduces Series Inductance ‘ESL’ by  50% • Decoupling and noise suppression in high-speed circuits • Improved response time in power circuits • Reduce the number of decoupling components used • Reduce PCB size - costs and component placement costs! • Operating Temperature Range: -55°C to +105°C • Capacitance Range 68uF to 560uF • Rated Voltage Range: 2.0V, 2.5V, 4.0V & 6.3VDC • +260°C Reflow Soldering Compatible Bottom view of component • ADVANTAGES: • Stable with voltage, temperature and time • No voltage derating • No DC bias (weakness of MLCC) •  Reduce ripple voltage •  Eliminates piezoelectric ringing & singing • Reduce number of capacitors used

  10. Decoupling Capacitors Requirements L x T W ESL = k x ESL Reduction by 3-Terminal Structure 2-terminal NSP series (+) Anode The smaller the capacitor ESL, the smaller the impedance loop, and the faster the capacitor response in transferring energy to the load, and the better the high frequency noise suppression ability Bottom view of component ESL loop impedance (-) Cathode 3-terminal NSPL series (+) Anode ESL in loop impedance is represented by Bottom view of component (-) Cathode where k is a constant 3-terminal NSPL has  50% lower ESL than standard 2-terminal NSP series

  11. Decoupling Capacitors Requirements 2 1.5 NSP181M2.5D6ZATRF 2.5V 180uF NSPL181M2.5D5YATRF 2.5V 180uF 1 ESL (nH) 0.5 0603 Size MLCC X5R 6.3V 22uF 0 0.1 0.1 10 10 0.01 1 100 Frequency (MHz) Typical ESL comparison between NSPL, NSP and MLCC  3-Terminal NSPL has low ESL, close to ESL of 0603 size MLCC

  12. Decoupling Capacitors Requirements 0.1 Impedance (Ohm) 0.01 0.001 0.01 1 100 0.1 10 Frequency (MHz) Typical Impedance (Z) comparison between NSPL, NSP and MLCC  3-Terminal NSPL has low Impedance (Z) over wide frequency range NSPL181M2.5D5YATRF 2.5V 180uF NSP181M2.5D6ZATRF 2.5V 180uF 0603 Size MLCC X5R 6.3V 22uF

  13. Decoupling Capacitors Requirements 2 1.5 1 ESL (nH) 0.5 0 0.1 1 10 100 Frequency (MHz) Typical ESL example for each thickness: 1.1mm, 1.4mm and 1.9mm NSPL471M2D6YATRF 2.0V 470uF, 1.9mmT NSPL331M2D1YATRF 2.0V 330uF, 1.4mmT NSPL221M2D5YATRF 2.0V 220uF, 1.1mmT

  14. Decoupling Capacitors Requirements 0.1 NSPL221M2D5YATRF 2.0V 220uF, 1.1mmT 0.01 ESR (Ohm) NSPL331M2D1YATRF 2.0V 330uF, 1.4mmT NSPL471M2D6YATRF 2.0V 470uF, 1.9mmT 0.001 0.01 0.1 1 10 100 Frequency (MHz) Low ESR performance for NSPL series; 220uF, 330uF & 470uF

  15. Decoupling Capacitors Requirements High frequency noise High ESL Better: lower noise Best: lowest noise NSPL Lowest ESL

  16. Summary Decoupling Capacitors Requirements - Summary • All decoupling capacitors should connect to a large area low impedance ground plane through a via or short trace to minimize inductance. • Reducing the ESL of the capacitor bank, results in better ‘faster’ capacitor bank that speeds energy transfer to the load. • The strategy is to place the 'fastest' low ESL capacitors as close to the load as possible, as physically close to the power pins of the chip as is possible • Mounted inductance is minimized by locating Vdd and Gnd vias close to each other and minimizing the length of via from the pad to the power planes.

  17. Q & A Open Discussion NIC has broad offering in Performance Passives Additional Information Needed? Need Samples? Technical Support: tpmg@niccompcom Sales Support: sales@niccomp.com • European Engineering Support • North America Engineering Support • SE Asia Engineering Support

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