By Thomas Kuehl – Senior Applications Engineer Precision Analog – Linear Applications Engineering

1. Analog Electronics Class 11Understanding and Protecting Against Electrical Overstress (EOS) of Operational-Amplifiers By Thomas Kuehl – Senior Applications Engineer Precision Analog – Linear Applications Engineering

2. This is your IC

3. This is your IC after an EOS event!

4. ESD and EOS definitions Amplifier input range ESD models Internal ESD and consequently EOS protection circuits Amplifier EOS operating situations External EOS protection Presentation Subjects

5. Electrostatic Discharge (ESD) – The transfer of electrostatic charge between bodies or surfaces at different electrostatic potential. Electrical Over Stress (EOS) – The exposure of an item to current or voltage beyond its maximum ratings. ESD and EOS: What’s the difference? ESD High voltage (kV’s) Short duration event (1-100ns) Fast edges Low power Out of circuit event EOS Low voltage >Vs Longer duration event Low power In-circuit event

6. Two very different environments ESD EOS 10V 0V

7. Input voltage range of an op-amp + +2kV– +100V ESD protect region In-circuit max positive ≈ OPA735 low Drift CMOS Op-amp Safe with Rs +5.5V +5.0V Pos Safe Non-linear input Pos rail +3.5V CMV input range * Input voltage 0V -0.1V -0.5V Neg rail Neg safe Safe with Rs -5.0V ≈ In-circuit max negative -100V– -2kV ESD protect region _ * Selected to limit input current to 10mA max.

8. ESD Stress Models

9. Human Body model Rdut is “on” resistance of an ESD protection circuit

10. Machine Model Rdut is “on” resistance of an ESD protection circuit

11. CDM - ESD by induction

12. Common input/output ESD protection circuits Input steering diodes CMOS input/output protection Vcer input clamp IC level SCR model is more complex

13. Supply clamp circuits NPN bipolar on high-speed process ≈ ON → ← OFF

14. NMOS parasitic bipolar transistor Gate Source (emitter) Drain (collector) n n IDS IC p Isub Rsub Sub (base) P-sub/epi

15. A commonly applied ESD protection method for analog integrated circuits Input protection Output protection ultra low leakage diodes Power supply absorption device

16. INA168 ESD cell layouts Input pin ESD2 N-sinker – BL ESD1 NPN B-E Supply clamp NPN transistor / resistor Output pin ESD7 NPN B-E ESD8 N-sinker – BL

17. The ESD protection paths V+ pin at GND Vout at GND ESD pulse source V- pin at GND

18. Input overdrive may activate ESD protection circuits VG1 + VG2 sum may activate ESD circuit on peaks

19. ESD cell paths may be activated during an EOS event * T1 can become a near short between supplies! Intended signal Input EOS source * *may no longer represent a near-zero impedance at high frequencies

20. A supply clamp transistor failure during resulting from an input EOS/ESD event Vcer clamp transistor

21. EOS-related CMOS operational-amplifier field failures • TI quad CMOS operational amplifier failing unexpectedly in air conditioner application • TI FA report indicated the operational amplifier die had carbonized material on die and pin 4 (V+) to pin 11 (V-) short • EOS analysis of the customer application input and output ESD circuits did not reveal any likely candidates

22. 20 Vpk EOS on V+ line EOS-related CMOS operational-amplifier field failures • A request for the Field Applications Engineers to observe and monitor the amplifier pins during the various operational cycles was made and provided • They found that a 20 Vpk pulse was appearing on the V+ line during operation of the air conditioner. The nominal supply voltage was +5 V • The EOS was causing either the supply-to-supply ESD clamp to break down, or voltage breakdown of the amplifier transistor structures • A higher voltage operational amplifier and a transient voltage suppressor on the V+ line were recommended

23. Input current limiting by external series-R Where does the 10mA IOVERLOAD maximum originate?

24. Parasitic circuit latch testing Current injection latch test The continuous input overload current is set to < 1/10th the JEDEC maximum latch test current(t ≤ 10ms)

25. Watch Vin during power up! Iin excessively high while supply ramps

26. INA Input protection

27. Excessive differential input over-voltage Possible occurrences • When operating an operational amplifier as a comparator • During slewing Bipolar input operational amplifier 90% Input-output voltage difference SR = 2.3V/us 10% Plot for illustrative purposes only!

28. OPA277 input-to-input differential over-voltage protection modern bipolar op-amps have input clamps Iin 20mA max VG1 = 2VD + (Iin R1) + Vo If VO = 0V, then: Iin = (VG1 – 2VD) ∕ R1

29. Input overdrive of CMOS rail-to-rail IO chopper amplifiers • When Vin exceeds a Vcm maximum Vo is forced to an output rail level • The op-amp is forced outside of its linear operating range • The feedback loop collapses and an input differential voltage develops • One clamp diode or the other becomes forward biased and the input bias current can increase tremendously • This may limit the use of this type of operational amplifier as a comparator Back-to-back clamp diodes are inherent and internal to the chopper switch structures

30. Overload Recovery Auto-zero CMOS Operational-amplifiers Positive input +50mV 0mV OPA335 Av = -50V/V 0V Negative output ≥ -2.5V Negative input 0mV -50mV ≤ 2.5V Positive output 0V Vin ≥ Vs / Gain

31. Output inversion during input overdrive +4.5V VG1 -0.5V +4.5V VM1 0V Output inversion

32. Supply pin over-voltage protection • Smoothing a transient • with an RLC filter • Transient amplitude effectively reduced • Ringing dependent on RLC values and load R • Amplifier PSRR becomes important

33. Supply pin over-voltage protection • Transient voltage suppression (TVS) diode • 6.8V- 550V reverse standoff voltage • Unidirectional & bidirectional models • Ppk = 1.5kW (10 x 1000us) @ 25C • Cj ≥ 1nF @ 20V • Littlefuse no. 1.5KE6.8, etc.

34. Supply pin over-voltage protection • Features • Multilayer ceramic construction • Operating voltage range VM(DC) = 5.5 to 120V • Non-repetitive surge current (8/ 20us) • Non-repetitive energy (10/ 1000us) • response time <1ns for zinc oxide • Inherent bidirectional clamping • Wider temperature range and flatter response • than solid-state TVS

35. Externally connected input protection devices Transient voltage suppressors For CMOS, bipolar and SiGe Features: Available from 5.6 to 18V DC working voltage ≤ 18V AC working voltage ≤ 14V Turn-on-time <1ns Repetitive spike capability uA J A pF

36. Externally connected input protection devices

37. Externally connected input protection devices Schottky diodes provide enhanced input protection • Features: • Forward voltage VF≤ 380mV, IF= 1mA • Forward current IF = 200mA max (cont.) • Leakage current IR≤ 100nA, VR = 30V • Diode capacitance Ctot ≤ 5pF, VR = 0V

38. Externally connected input protection devices

39. Power Line Communications (PLC) EOS environment – IEC61000-4-5 Open-circuit surge pulse test 4kV, 1.5us tfront, 50us thalf-value

40. PLC – EOS protectionActual protection scheme will vary with application and layout High voltage MOV and low-voltage TVS clamping Fast rectifier and Schottky clamps The internal output ESD cell is unlikely to withstand the open-circuit HV pulse - latching is probable

41. EOS and ESD events may activate ESD protection but result in different outcomes Internal ESD circuits may sufficiently handle EOS Be aware of unique EOS situations such as power up and input slewing External EOS protection circuits will be required if device damage is likely to occur without it In Summary