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Simulation & Synthesis

Simulation & Synthesis. of UART HD-6402 using VHDL. Presented by. [02-384] Deepak Patel. Scope of our Project. VLSI and its Emergence. Chip Complexity. 1975: transistor size = 10  m. 1985: transistor size = 2  m. 1995: transistor size = 0.4  m. Introduction to VHDL. Design Process.

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Simulation & Synthesis

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  1. Simulation & Synthesis of UART HD-6402 using VHDL Presented by [02-384] Deepak Patel

  2. Scope of our Project

  3. VLSI and its Emergence

  4. Chip Complexity 1975: transistor size = 10m 1985: transistor size = 2m 1995: transistor size = 0.4m

  5. Introduction to VHDL

  6. Design Process

  7. Requiredproduct Designspecifications Initial design Simulation Redesign No Design correct? Yes Prototype implementation Makecorrections Yes Testing Minorerrors? No No Meetsspecifications? Yes Finishedproduct

  8. Concept of Design Review Design Specifications Simulation RTL Simulation Synthesis Description Verify Synthesis Results Timing Analysis Implementation( FPGAs , ASICs )

  9. UART Basics for our project

  10. Receiver Decoder Source Transmitter Encoder Destination Communication system Channel

  11. 8 Data Bits Stop Bit Start Bit Mark Space Asynchronous Communication

  12. U niversal A synchronous R eceiver T ransmitter What is UART ?

  13. External Device Basic UART Interface PARALLEL DATA BUS U A R T mP

  14. Computer and mP systems often send/receive data in parallel format External devices are capable of communicating only serially To convert the parallel data from mP systems to serial data to external devices Or vice-versa. It is necessary to have an interfacing device. Need for UART

  15. Block Diagram of UART

  16. Block Diagram of UART

  17. Control Word

  18. Advantages of Implementing UART using VHDL

  19. How Stuff works ???

  20. CLS2 CLS1 DATA LENGTH 0 0 5 BITS 0 1 6 BITS 1 0 7 BITS 1 1 8 BITS PARITY FUNCTION CLS2 CLS1 8 BIT DATA PARITY GENERATOR PARITY BIT

  21. TRANSMITTER P1: If CRL is High load CONTROLWORD P2: 0 to 5 Bits 1 to 2 Bits 0 or 1 Bit 5 to 8 Bits 1 Bit

  22. P3: Generation of TRE, TBRE. If CTRLWORD is 000X0 counter = 8If CTRLWORD is 000X1 counter = 9Shifting 12 bit contents to right bit by bit.Transmit serial Data at TRO pin.

  23. RECEIVER P1: If CRL is High load CONTROLWORD.Receive data from transmitter bit by bit. P2: To see that data is not overwritten with the help of DR pin.To store each bit serially in a register. Data In Data Out If CONTROLWORD is 0001X => 1 start 5 data 0 parity 1 stopSo 5th bit is checked and if 0 then DR is set

  24. P3:In it valid data is send into receiver register and extra zeros are padded. If CONTROLWORD is 0001X =>1 start 5 data 0 parity 1 stop Data In Data Out So valid data bits are from 10 to 6. P4: In it PE, FE, OE are generated. If CTRLWORD is XX101- check 9th bit. If CTRLWORD is XX001- check 10th bit. If CTRLWORD is XX0XX- check 11th bit for Stop bit. If CTRLWORD is XX1XX- check 10th and 11th bit for Stop bit. P5: Sends 8 Bit data to RBR and sends error output to output pins.

  25. Thank you

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