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SCIPP R&D on Long Shaping-Time Electronics

SCIPP R&D on Long Shaping-Time Electronics. SLAC SiD Workshop October 26-28, 2006 Bruce Schumm. The SCIPP/UCSC ILC HARDWARE GROUP. Faculty/Senior Vitaliy Fadeyev Alex Grillo Bruce Schumm Abe Seiden. Post-Docs Jurgen Kroseberg. Students Greg Horn Gabriel Saffier-Ewing.

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SCIPP R&D on Long Shaping-Time Electronics

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  1. SCIPP R&D on Long Shaping-Time Electronics SLAC SiD Workshop October 26-28, 2006 Bruce Schumm

  2. The SCIPP/UCSC ILC HARDWARE GROUP Faculty/Senior Vitaliy Fadeyev Alex Grillo Bruce Schumm Abe Seiden Post-Docs Jurgen Kroseberg Students Greg Horn Gabriel Saffier-Ewing Lead Engineer: Ned Spencer Technical Staff: Max Wilder, Forest Martinez-McKinney (Students are undergraduates from physics)

  3. Alternative: shorter ladders, but better point resolution • The LSTFE approach would be well suited to use in short-strip applications, and would offer several potential advantages relative to other approaches • Optimized for LC tracking (less complex) • More efficient data flow • No need for buffering Would require development of 2000 channel chip w/ bump bonding (should be solved by KPiX development)

  4. The LSTFE ASIC Process: TSMC 0.25 m CMOS ~1 s shaping time; analog readout is Time-Over-Thresh

  5. 128 mip 1 mip Operating point threshold Readout threshold 1/4 mip

  6. Electronics Simulation Detector: 167 cm ladder, 50 m pitch, 50 m readout Analog Measurement: Employs time-over-threshold with 400 ns clock period; lookup table provides conversions back into analog pulse height (as for actual data) RMS Gaussian Fit Essential tool for design of front-end ASIC Detector Resolution (units of 10m)

  7. Li Hi Li+1 Hi+1 Li+2 Hi+2 Li+3 Hi+3 Li+4 Hi+4 Li+5 Hi+5 Li+6 Hi+6 Proposed LSTFE Back-End Architecture Low Comparator Leading-Edge-Enable Domain 8:1 Multi-plexing (clock = 50 ns) FIFO (Leading and trailing transitions) Event Time Clock Period  = 400 nsec

  8. DIGITAL ARCHITECTURE: FPGA DEVELOPMENT Design permits real-time accumulation and readout of hit information, with dead time limited only by amplifier shaping time

  9. INITIAL RESULTS LSTFE-2 chip mounted on readout board FPGA-based control and data-acquisition system

  10. Qin= 1.0 fC Qin= 0.5 fC Comparator S Curves Vary threshold for given input charge Read out system with FPG-based DAQ Get 1-erf(threshold) with 50% point giving response, and width giving noise Qin= 1.5 fC Qin= 2.0 fC Stable behavior to Vthresh < 10% of min-i Qin= 2.5 fC Qin= 3.0 fC

  11. Noise vs. Capacitance (at shape = 1.2 s) Loaded with Capacitor Measured dependence is (noise in equivalent electrons) noise = 375 + 8.9*C with C in pF. Connected to Ladder Noise is approximately 30% worse; are currently exploring long shaping-time shielding requirements Expected Observed 1 meter

  12. Power Cycling • As designed: Achieve 40 msec turn-on due to protection diode leakage • Injecting small (< 1nA) current: Achieve 0.9 msec Power Control LSTFE2 will incorporate active feedback to maintain bias levels of isolated circuitry when chip is “off”. Preamp Response Shaper Response

  13. LSTFE2 • The LSTFE2 is currently under development; submission expected by end of year • Retain 1.0-1.5 s shaping time • Further S/N optimization (still geared towards long ladders) • “Off” state feedback to achieve power cycling goal (< 1 msec switch-on) • 64-128 channels, with multiplexing of compar-ator outputs (pad geometry)

  14. SCIPP Simulation Studies for the SiD Design SLAC SiD Workshop October 26-28, 2006 Bruce Schumm

  15. Personnel: B.S. plus three junior physics majors Lori Stevens (worked over summer) Tyler Rice (work over summer) Chris Meyer (new) • We are: • continuing the study of the use of Tim Nelson’s AxialBarrelTracker as a clean-up algorithm (Lori, Tyler) • trying to implement and verify new tracking algorithms (which ones?) - Chris

  16. AxialBarrelTracker Studies • Still “cheating”: eliminating all hits from the 95% of tracks that originate within 2cm of origin • Trying to do full classification of remaining hits (non-prompt tracks, loopers, backgrounds, etc.) • Looking for remaining non-prompt tracks with pt>0.75 GeV/c and |cos| < 0.5 • Have verified that circle-fit Chisq behaves like a chisq (tracking conventions?); use chisq cut, but not very effective • Require 4 or more hits; found track can have at most one hit from a different MCTRUTH source; otherwise labeled as fake

  17. e+e- qq at sqrt(s) = 500 GeV 263 “findable” tracks • 272 “fake” tracks • 271 with 4 hits • 1 with 5 hits Very preliminary! • 214 “found” (MCTRUTH • Associated) tracks • 97 with 4 hits • 117 with 5 hits • 44% efficient • 99% pure (!!??) Is this correct? What about an 8-layer tracker?

  18. Algorithm Verification Chris Meyer in process of learning to run code developed by Michael Young to study recon/ fitter performance. NOTE: The studies shown here for VXD- BasedReco are old and are shown for demon-stration purposes only!

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