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COMPUTER ARCHITECTURE

COMPUTER ARCHITECTURE. Instructions - Addressing Modes. (Based on text: David A. Patterson & John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface , 3 rd Ed., Morgan Kaufmann, 2007 ). COURSE CONTENTS. Introduction Instructions Computer Arithmetic

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COMPUTER ARCHITECTURE

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  1. COMPUTER ARCHITECTURE Instructions - Addressing Modes (Based on text: David A. Patterson & John L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, 3rd Ed., Morgan Kaufmann, 2007)

  2. COURSE CONTENTS • Introduction • Instructions • Computer Arithmetic • Performance • Processor: Datapath • Processor: Control • Pipelining Techniques • Memory • Input/Output Devices

  3. Overview of MIPS • Simple instructions all 32 bits wide • Very structured, no unnecessary baggage • Only three instruction formats • Addresses are not 32 bits • How do we handle this with load and store instructions op rs rt rd shamt funct R I J op rs rt 16 bit address op 26 bit address

  4. Addresses in Branches and Jumps • Instructions: • bne $t4,$t5,LabelNext instruction is at Label if $t4≠$t5 • beq $t4,$t5,LabelNext instruction is at Label if $t4=$t5 • j LabelNext instruction is at Label • Formats: op rs rt 16 bit address I J op 26 bit address

  5. Addresses in Branches • Instructions: • bne $t4,$t5,LabelNext instruction is at Label if $t4≠$t5 • beq $t4,$t5,LabelNext instruction is at Label if $t4=$t5 • Formats: • Could specify a register (like lw and sw) and add it to address • Use Instruction Address Register (PC = program counter) • Most branches are local (principle of locality) • Jump instructions just use high order bits of PC • Address boundaries of 256 MB op rs rt 16 bit address I

  6. Addressing Modes • Register addressing • operand is in a register, e.g. add $s1, $s2, $s3 • Base or displacement addressing • operand at memory location [register + constant (base)]e.g. 2nd operand in lw $t0, 200($s1) • Immediate addressing • operand is a constant within instruction e.g. 3rd operand in addi $s1, $s2, 10 • PC-relative addressing • address = PC (+4) + constant in instruction (*4)e.g. 3rd operand in bne $s0, $s1, Exit • Pseudodirect addressing • address = PC upper bits concatenated with 26-bit address in inst.

  7. 1 . I m m e d i a t e a d d r e s s i n g o p r s r t I m m e d i a t e 2 . R e g i s t e r a d d r e s s i n g o p r s r t r d . . . f u n c t R e g i s t e r s R e g i s t e r 3 . B a s e a d d r e s s i n g M e m o r y o p r s r t A d d r e s s + B y t e H a l f w o r d W o r d R e g i s t e r Addressing Modes

  8. 4 . P C - r e l a t i v e a d d r e s s i n g M e m o r y o p r s r t A d d r e s s + W o r d P C 5 . P s e u d o d i r e c t a d d r e s s i n g M e m o r y o p A d d r e s s W o r d P C Addressing Modes

  9. Other Issues • MIPS assembler accepts this pseudoinstruction even though it is not found in MIPS architecture: • move $t0, $t1 #$t0  $t1 • it translates it to: add $t0, $zero, $t1 • Other pseudoinstructions: mult, blt, bge, etc. • Assembler keeps track of addresses of labels in symbol table • Details of assembler, linker, & loader are given in Appendix A • Details of MIPS instruction set & architecture in Appendix A • % frequency of instruction execution

  10. Instruction Set Architecture Classes • Use of accumulator (a default register): • 1 address instruction; e.g. add A: acc  acc + mem[A] • e.g. EDSAC, IBM 701, DEC PDP-8, MC 6800, Intel 8008 • Use of stack: • 0 address instruction; e.g. add: top(stack)  top(stack) + next_top(stack) • Use of general purpose registers: • 2 address instruction; e.g. add A, B: A  A + B • 3 address instruction; e.g. add A,B,C: A  B + C • load/store (reg/reg): e.g. MIPS, Sun’s SPARC, MC PowerPC, DEC Alpha • memory/memory: e.g. DEC VAX • memory/register: e.g. DEC VAX, IBM 360, DEC PDP-11, MC 68000, Intel 80386

  11. RISC vs. CISC • RISC -- Reduced Instruction Set Computer -- philosophy (instruction sets measured by how well compilers used them) • fixed instruction lengths • load/store instruction sets • all operands of ALU instructions are in registers • limited addressing modes • limited operations • e.g. MIPS, Sun SPARC, HP PA-RISC, PowerPC (AIM), ARM, Renesas Tech. SuperH (by Hitachi), ARM/Thumb, etc. • CISC – Complex Instruction Set Computer -- Implies • fewer instructions in the set • larger register file • longer programs • good for pipelining • simpler control

  12. Chapter Summary • Instruction Type • Instruction Format • RISC Design Principles • Assembly vs. Machine Language • Addressing Modes • Classes of Instruction Set Architecture • RISC vs. CISC

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