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An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes

Learn about an improved LDPC decoding method, Split-Row Threshold Decoding, and its impact on error performance results. Explore the implementation, threshold selection, and error performance comparisons. Improve LDPC decoding efficiency and reduce complexity with this innovative approach.

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An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes

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  1. An Improved Split-Row Threshold Decoding Algorithm for LDPC Codes Tinoosh Mohsenin, Dean Truong and Bevan M. Baas VLSI Computation Lab, ECE Department University of California, Davis

  2. Outline • Introduction LDPC Decoding • Goals and Key Features • Split-Row Threshold Decoding Method • Error Performance Results • Split-Row Threshold Decoder Implementation and Results • Conclusion

  3. LDPC Decoding • Message passing decoding • LDPC decoding challenges • High interconnect complexity for large number of processing nodes • Large delay, area, and power dissipation caused by long and global wire

  4. Outline • Introduction to LDPC Decoding • Goals and Key Features • Split-Row Threshold Decoding Method • Error Performance Results • Split-Row Threshold Decoder Implementation and Results • Conclusion

  5. LDPC Decoder Design Goals and Features • Key goals • Very high throughput and high energy efficiency • Area efficient (small circuit area) • Well suited for long-length and large row weight LDPC codes • Easy implementation with automatic CAD tools • Good error performance • Split-Row decoding key features • Reduced interconnect complexity • Reduced processor complexity T. Mohsenin and B. Baas, “Split-row: A reduced complexity, high throughput LDPC decoder architecture,” in ICCD, 2006 T. Mohsenin and B. Baas, “High-throughput LDPC decoders using a multiple Split- Row method,” in ICASSP, 2007

  6. 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 H = 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 H H split - sp 0 split - sp 1 C 1 C 1 sp 1 sp 0 V 10 V 8 V 3 V 5 Standard vs. Split-Row Decoding standard decoding Split-Row decoding reduction of check processor area reduction of input wires to check processor

  7. MinSum vs. MinSum Split-Row Sign Magnitude MinSum: MinSum Split-Row:

  8. Outline • Introduction to LDPC Decoding • Goals and Key Features • Split-Row Threshold Decoding Method • Error Performance Results • Split-Row Threshold Decoder Implementation and Results • Conclusion

  9. MinSum Split-Row Threshold Algorithm • A signal (Threshold_en) is passed from each partition, which indicates whether a partition has a minimum less than a given threshold (T). • Based on Threshold_en status, the check nodes take as their minimum of their own local Min or T. • Optimum threshold value (T) is obtained by empirical simulations Threshold_en Sp1=1 Threshold_en Sp0=0 MinSum Split-Row Threshold:

  10. Impact of Threshold Selection 15 decoding iterations SNR=4.2 dB • (6,32) (2048,1723) LDPC Code • Optimum threshold (T) is independent of SNR and decoding iteration Optimum T=0.2 Optimum T=0.2

  11. Outline • Introduction to LDPC Decoding • Goals and Key Features • Split-Row Threshold Decoding Method • Error Performance Results • Split-Row Threshold Decoder Implementation and Results • Conclusion

  12. Error Performance for (16,4) (1536,1155) LDPC Code • In the Plot: • BPSK modulation • AWGN channel • Based on 80 error blocks • Maximum 15 iterations • SPA: Sum Product Algorithm • MS: MinSum Normalized • For MS Split-Row Threshold T=0.3 0.08dB 0.42 dB

  13. 32/Spn variable nodes Multi-Split-Row Threshold Decoding • Divide parity check matrix to Spn (Spn>2) partitions • Partitioning can be arbitrary so long as there are at least two variable nodes per partition • Example: (6,32) (2048,1723) LDPC Code

  14. Error Performance for (2048,1723) 10GBASE-T Code • MS Split-Row-2 Threshold is 0.07 dB away from MS • MS Split-Row-16 Threshold is 0.22 dB away from MS and is 0.12 dB better than Split-Row-2 Original. 0.22 dB 0.12 dB

  15. Outline • Introduction to LDPC Decoding • Goals and Key Features • Split-Row Threshold Decoding Method • Error Performance Results • Split-Row Threshold Decoder Implementation and Results • Conclusion

  16. Comparison of Decoders (6,32) (2048,1723) 10GBASE-T code with 15 decoding iterations.

  17. Conclusion • Split-Row Threshold algorithm improves the error performance when compared with original Split-Row. • Split-Row Threshold allows for high level of partitionings without losing significant error performance. • Higher level of partitioning reduces the number of connections between check and variable processors. This results in a higher logic utilization, smaller and faster circuits. • We can meet the demands of high speed applications while obtaining very low area when compared to standard decoding.

  18. Acknowledgements • Support • ST Microelectronics • NSF Grant 430090 and CAREER award 546907 • Intel • SRC GRC Grant 1598 and CSR Grant 1659 • Intellasys • UC Micro • SEM • Special thanks • Professor Shu Lin

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