Download
1 / 41
410 likes | 526 Views
Lecture 2: Processor, program cycle, interrupts, system bus Piotr Bilski. Computer Architecture. von Neumann Machine. CPU. I/O devices. AC. I/O AR. ALU. MBR. I/O BR. Internal bus. Main memory. MAR. CU. PC. IR. Program.
E N D
Lecture 2: Processor, program cycle, interrupts, system bus Piotr Bilski Computer Architecture
von Neumann Machine CPU I/O devices AC I/O AR ALU MBR I/O BR Internal bus Main memory MAR CU PC IR
Program • Program is a set of instructions which, executed is a predefined order, assures processing of the information in a desired way. • Instruction is a machine word, containing information about the executed instruction and memory location, where arguments, results and the next instruction are stored.
Requirements for the computer system executing program (von Neumann) Computer system should: • Have finite and functionally coherent instruction list; • Be able to insert program into the computer system using external devices and store instructions in the memory in the identical way as data; • Store data and instructions in the memory in a way that they were equally accessible for the processor (by the addresses in the memory); • Be able to process the information by sequential reading of the instructions from the memory and executing them by the processor .
X1 X2 X3 X4 X1 X2 X3 X4 Y1 Y2 Y1 Y2 Program vs hardware „program” control Hard-wired program 0000: move 4 0001: add 5 0010: store 6 0011: stop
Interrupt execution Instruction fetching Instruction execution Interrupts valid? Computer operation Interrupt cycle Fetch cycle Execution cycle YES NO START STOP
Register transfer language • Symbols of capital letters stand for the content • M – memory • A, MAR etc. – register • writing • ( ) – address • 0:7 – range of bits of the memory word or registry, used in the operation For instance: MAR PC MBR M(MAR)
Instruction fetching cycle • Program counter (PC) stores address of the next instruction to acquire (at the beginning it is so called entry point) • Processor fetches instruction from the address pointed by PC • Value of the PC is increased by 1 (unless something else is required - jump) • Instruction is loaded into the instruction register (IR) • Processor decodes instruction and executes operation pointed by it
Illustration of the instruction fetching cycle Entry point Address Content • Move 104 • Add 105 • Store 106 • Stop • 3 • 5 AC MBR ALU MAR PC CU PC IR 100 MAR ADDRESS BUS
Illustration of the instruction fetching cycle (cont.) DATA BUS MBR M(MAR) Move 104 Address Content • Move 104 • Add 105 • Store 106 • Stop • 3 • 5 AC MBR ALU READ CU PC IR CONTROL BUS MAR 101 ADDRESS BUS
Illustration of the instruction fetching cycle (cont.) DATA BUS Move 104 Address Content • Move 104 • Add 105 • Store 106 • Stop • 3 • 5 AC MBR ALU PC PC + 1 READ CU PC IR CONTROL BUS 101 MAR 100 ADDRESS BUS
Illustration of the instruction fetching cycle (cont.) DATA BUS Move 104 Address Content • Move 104 • Add 105 • Store 106 • Stop • 3 • 5 AC MBR ALU IR MBR Move 104 READ CU PC IR CONTROL BUS 101 MAR 100 ADDRESS BUS
Illustration of the instruction fetching cycle (cont.) DATA BUS Move 104 Address Content • Move 104 • Add 105 • Store 106 • Stop • 3 • 5 AC MBR ALU CU IR Move 104 READ CU PC IR CONTROL BUS 101 MAR 100 ADDRESS BUS
Instruction execution cycle • Processor-memory • data transfer between CPU and memory • Processor – input/output • data transfer between CPU and input/output module • Data processing • Arithmetic or logical operations on the data • Change of the instruction execution order (for example, jump) • Control • Combination of the above
Illustration of the instruction execution cycle (cont.) Data BUS MBR M(104) 3 Address Content • Move 104 • Add 105 • Store 106 • Stop • 3 • 5 AC MBR AC MBR ALU MAR IR(104) Move 104 READ CU PC IR CONTROL BUS 101 MAR 104 104 ADDRESS BUS
Next instruction fetching cycle DATA BUS MBR M(101) Add 105 Address Content • Move 104 • Add 105 • Store 106 • Stop • 3 • 5 AC MBR ALU MAR PC READ CU PC IR CONTROL BUS 101 MAR 101 ADDRESS BUS
Next instruction fetching cycle (cont.) DATA BUS Add 105 Address Content • Move 104 • Add 105 • Store 106 • Stop • 3 • 5 AC MBR ALU IR MBR CU IR Add 105 READ CU PC IR CONTROL BUS 101 MAR 101 ADDRESS BUS
Instruction format 0 3 4 15 Operation code Address 0 1 15 Size Sign instruction argument For example Move 104 - 0101000001101000
State graph of the instruction cycle Calculate argument addr. Fetching argument Fetch instr. Many arguments Many results Instr. decode Calculate argument addr. Calculate instr. address Saving argument Data operation No interrupts Return to data Instruction executed, fetch the next one Check for interrupts Interrupt execution
Interrupts • Mechanism allowing to disturb the original execution order by the other system components • Programmed • For example, overflow, divide by zero • Clock-generated • Generated by the internal processor clock • Used for process scheduling • Input/Output • From the I/O controller • Hardware failure • Memory parity error
Application of the interrupts User program User program I/O program I/O Program 1 1 4 4 WRITE WRITE I/O instruction I/O instruction 2a @ 2b 2 Interrupt execution program 5 WRITE WRITE Stop 3a @ 3b 5 3 Stop
Interrupt cycle • Processor checks periodically, if the interrupt ocurred • It is shown by the interrupt signal • If no interrupt occured, the next instruction is fetched • If the interrupt occured: • The executed program is suspended • Its context is saved • Program counter is set to the address of the first instruction of the interrupt execution program • Interrupt is processed • After that, the previous context is loaded to the CPU and the user program is executed from the point it was suspended
Multiple interrupts Two ways of the multiple interrupts execution exist • Blocked interrupts • Processor ignores other interrupts while the current interrupt is processed • Interrupts are queued and after the current interrupt is processed, the next one (if exists) is processed • Interrupts are executed in the sequence they occured • Priorities • Execution of the low priority interrupt can be suspended by the higher priority interrupt • After execution of the higher priority interrupt the execution of the low priority interrupt is continued
Multiple interrupts execution Sequential execution Priority execution User program User program Interrupt nr 1 Interrupt nr 1 Interrupt nr 2 Interrupt nr 2
Data flow in the computer modules read write MEMORY ADRESS DATA N words DATA read write INPUT / OUTPUT MODULE Internal data ADRESS External data Internal data M ports INT. External data ADRESS INSTR. PROCESSOR DATA DATA INT. INT.
BUS • The highway to allow communication between the devices • Includes multiple trails of the three types: data, address and control • Breadth of the bus is the maximum number of bits, which can be transferred between the modules
The main buses • ISA (1985) • PCI (1993) • AGP 1x/2x (1997-1998) • AGP 4x (1999) • AGP 8x (2002) • PCI Express (2004) • SCSI (1979) • Industrial busses (PROFIBUS, IEC-625)
How does it work? Communication between the two modules Sending data: 1. Accessing the bus 2. transferring the data Receiving data: 3. Accessing the bus 4. Informing about the need to acquire data (using control lines) 5. Awaiting the incoming data
Buses categories Application • Specialized • Multiplexed Arbitration method • Centralized • Distributed Time synchronization • Synchronous • Asynchronous
PCI bus • Proposed by Intel in 1990 • Work frequency: 66 MHz • Works in 32 or 64-bit configuration • Communication between the processor and the memory using bridges • Valid signal lines: • system (np. clock, reset) • Address and data (32) • Interface control • Arbitration (individual!) • Error information
PCI Express bus • Parallel bus architecture • Introducing switches • Backward compatibility with PCI • Scaleable bandwidth of the bus – from 1x to 32x (depending on the used channels/slots) • Speed of 250 MB/s for the single slot (for the graphic card 16x PCIe it is 4 GB/s)
