Variables and Functions

1. Variables and Functions Revisited

2. Variables • What are variables? Representatives of state of signal(s)/container(s)/input(s) An electrical voltage Sometimes a single voltage sometimes multiple voltages • What are variables used for? Numbers/conditions/arguments Decision making Calculations

3. How Do we Represent Variables ? • X, x1, s, f, • sw(2)

4. How Do we Use Variablesto Make Decisions? Logic Networks Logic Statements By putting the voltages through a set of transistor switches

5. How Do we RepresentLogic Networks? • Graphically • Block Diagrams • Schematics • Word Descriptions • Sentences • VHDL

6. Declaring Variables in VHDL selct : IN STD_LOGIC; datain : IN STD_LOGIC_VECTOR(7 DOWNTO 0); datain : IN STD_LOGIC_VECTOR(0 TO 7); • What’s the difference? Consider the statement: datain AND “01111111”; Which bit do you get?

7. Manipulating Variables in VHDL ENTITY ifElseLab ISPORT (  SW        : IN    STD_LOGIC_VECTOR(5 DOWNTO 0);        LEDG    : OUT    STD_LOGIC_VECTOR(0 DOWNTO 0)     );END ifElseLab;ARCHITECTURE function_of_example OF ifElseLab ISBEGIN    PROCESS(SW(0), SW(1), SW(2), SW(3), SW(4), SW(5))    BEGIN        IF SW(0) = '0' AND SW(1) = '0' THEN            LEDG(0)<= SW(2);         ELSIF SW(0) = '1' AND SW(1) = '0' THEN

8. ENTITY ifElseLab IS PORT (  SW        : IN    STD_LOGIC_VECTOR(5 DOWNTO 0);        LEDG   : OUT    STD_LOGIC_VECTOR(0 DOWNTO 0)      ); END ifElseLab;ARCHITECTURE function_of_example OF ifElseLab IS SIGNAL sel : STD_LOGIC_VECTOR(0 to 1); BEGINsel <= sw(1) & sw(0);     PROCESS(sel, SW(2), SW(3), SW(4), SW(5))    BEGIN        IF sel = “00” THEN            LEDG(0)<= SW(2);         ELSIF sel = “01” THEN

9. ENTITY f4to1MUXVHDL IS    PORT (    sw2, sw3, sw4, sw5    : IN     STD_LOGIC ;            sw                            : IN     STD_LOGIC_VECTOR(0 to 1);            f                            : OUT     STD_LOGIC ) ;END f4to1MUXVHDL ;ARCHITECTURE Behavior OF f4to1MUXVHDL IS    BEGIN    PROCESS ( sw2, sw3, sw4, sw5, sw )    BEGIN        CASE sw IS            WHEN "00" =>                f <= sw2;            WHEN "01" =>                f <= sw3;

10. ENTITY four_to_one_mux IS    PORT ( sw : IN STD_LOGIC_VECTOR(5 DOWNTO 0); ledg0 : OUT STD_LOGIC        );END four_to_one_mux;ARCHITECTURE bob OF four_to_one_mux IS    BEGIN        WITH sw SELECT            ledg0 <= w(0) WHEN "00",                     w(1) WHEN "01", Will this work? No, because the expression WHEN “00” has only 2 elements while the declared variable has 6 elements.

11. ENTITY four_to_one_mux IS    PORT ( sw : IN STD_LOGIC_VECTOR(5 DOWNTO 0); ledg0 : OUT STD_LOGIC        );END four_to_one_mux;ARCHITECTURE bob OF four_to_one_mux IS SIGNAL sel : STD_LOGIC_VECTOR(0 to 1);     BEGIN sel <= sw(1) & sw(0);         WITH sel SELECT            ledg0 <= w(0) WHEN "00",                      w(1) WHEN "01",