1 / 26

Wild Circuits

Wild Circuits. Investigating the Limits of MIN/MAX/AVG Circuits Brendan Juba Faculty Advisor: Manuel Blum Graduate Mentor: Ryan Williams. Definitions: MIN/MAX/AVG Circuits. unsatisfied. satisfied.

darby
Download Presentation

Wild Circuits

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Wild Circuits Investigating the Limits of MIN/MAX/AVG CircuitsBrendan Juba Faculty Advisor: Manuel BlumGraduate Mentor: Ryan Williams

  2. Definitions: MIN/MAX/AVG Circuits unsatisfied satisfied • We are given a circuit, C, with feedback, operating on real numbers from the closed interval [0,1]. • C contains • MIN, MAX, or AVG gates with two inputs • “Inputs” to the circuit that are hard-wired to either 0 or 1. • |C| denotes the number of gates of C • Here, |C| = 3 • When the output of a gate is the appropriate function of its inputs, we say that the gate is satisfied 1 0 0 MIN AVG 0 MAX 0 satisfied

  3. Definitions: MIN/MAX/AVG Circuits • Settings of the gate outputs from the interval [0,1] are value vectors • A value vector for C,v [0,1]|C| • The ith entry, vi, is the output of the ith gate. • We may also consider an update function, F: [0,1]|C|  [0,1]|C| • We are interested in two varieties: single-gate update functions and circuit-wide update functions: • A single gate update function replaces the output of a single designated gate with the correct output value. • We will call iterating over the single gate update functions “gate-by-gate update” • The circuit-wide update function simultaneously replaces the output of every gate with a value that is correct with respect to the old values 1 0 MIN AVG MAX

  4. Definition: Stable Circuit Problem • A vector v is stable iff every gate is satisfied. (F(v) = v) • Gate-by-gate update from the vector 0 obtains a stable vector in the limit.This is the minimum stable solution • We wish to find the minimum stable solution 1 0 1 0 unstable stable MIN MIN 0 0 1/2 1/2 AVG AVG MAX MAX 0 1/2

  5. Definition: STABLE CIRCUIT (Decision Problem) • We are given a circuit C, and some designated ith gate. In the minimum stable solution of C, s, “is si ≥ 1/2?” • If we can efficiently solve this decision problem, we can efficiently solve the function problem: we can find 2|C| bits of any si, which may be shown to be sufficient. • Inductively suppose we know the first k-1 bits of si to be v • Modify C: • (1-1/2k-v) requires k gates (1-v-1/2k) AVG ith gate • In the minimum stable solution, this new AVG gate’s output is above 1/2 iff the kth bit of si is a 1, so the decision problem tells us the kth bit of si • Ex: Suppose v = .011010, si = .0110101… (k = 7) thenAVG(si,1-1/2k-v) = (.0110101… + .1001011)/2 = .10000000… • If si = .0110100… then AVG(si,1-1/2k-v) = (.0110100… + .1001011)/2 = .01111111…

  6. Unique Solution Circuits x 0 • Replace any wire from x to y in the circuit with the construction on the right using m AVG gates • This circuit has a unique solution (Shapley, 1953) • Suppose the original circuit-wide update function is F, stable solutions are u and v • If ||u-v||∞= c, then it is easy to seec = ||u-v||= (1-1/2m)||F(u)-F(v)|| ≤ (1-1/2m)c • Clearly, c = 0. • These solutions turn out to be arbitrarily close to the minimum stable solutions (for appropriate m). AVG AVG AVG y

  7. STABLE CIRCUIT is in NPco-NP (Condon, 1992) • A nondeterministic machine M can, in polynomial time, on input circuit C, for gate i • Build a suitably close unique solution circuit C’ • It may be shown that damping by (1-1/25|C|) suffices • Guess the solution to C’ • Verify the guessed vector is a solution • Accept or reject, respectively, precisely when the value of gate i is above 1/2 (since C’ was close to C, either i is above 1/2 in neither, or it is above 1/2 in both)

  8. STABLE CIRCUIT is P-hard • If we use no AVG gates, the wires of the circuit will only carry 0 or 1 • It is immediate that we may use MIN as AND, MAX as OR • For any circuit with fixed inputs, we can construct a “complement” circuit • Switch 0 inputs with 1 inputs • Switch MIN gates with MAX gates • We can now negate by crossing a wire between the original and complement circuits • (In this AVG-free case, deciding the output is in P, too)

  9. Observations and Motivations • Our original motivation was to show STABLE CIRCUIT was hard for some class larger than P • If we apply gate-by-gate or circuit-wide update on arbitrary starting value vectors, we can obtain “interesting” circuits • One such “interesting” circuit is a binary counter • A circuit that halts conditionally would also be “interesting” • We do not necessarily obtain stable configurations of our circuits when starting from arbitrary value vectors -- this is not Stable Circuit • If we apply gate-by-gate or circuit-wide update on the value vector 0, can we obtain “interesting” circuits? • If so, the minimum stable solution is the configuration of the device after an unbounded amount of time!

  10. Can we obtain “interesting” circuits starting from 0? YES

  11. “Leapfrog” circuits • We assign each wire a “threshold” wire and interpret its value relative to that threshold • Above threshold: T • Below threshold: F • It is already clear that we still have AND and OR • There is also a construction for NOT (next slide) • If there are W wires which we wish to interpret relative to the same threshold, this gadget takes Θ(W) gates • NB: The circuits are still monotone! • As we update, a value may seem to rise or fall, as we follow it across different wires through the circuit • The value on any particular wire only rises as the gates of the circuit are updated

  12. NOT Gadget th x1 x0 x2 AVG AVG AVG MAX MAX MAX AVG AVG AVG MIN MIN MIN MIN MIN MIN MIN MIN MIN MAX MAX MAX MAX MAX MAX ~x0 th x0 x1 x2 th x1 x2

  13. Caveats • Assumptions: • All values above [below] threshold are equal • The values th, T, and F are all different • We may specify the update order for the gates of the circuit • Take each in turn: • Everything starts from zero and the property is preserved by our AND, OR, and NOT gates • We can push th above zero by means of an AVG gate • With feedback, we must also pass the other wires through AVG gates to preserve relative values • Update order doesn’t change the solution we approach

  14. Two-bit Counter Circuit 1 1 AVG AVG AVG AVG x0 x1 th NOT NOT MIN MIN MIN MIN MIN MIN MAX MAX MAX 1 1 AVG AVG AVG AVG AVG AVG 0 x0 x1 th

  15. Two-bit Counter Circuit 1 17/32 AVG x0 x1 th NOT NOT MIN MIN MIN MIN MIN MIN MAX MAX MAX 1 1 AVG AVG 1/2 x0 x1 th

  16. Two-bit Counter Circuit 1 781/ 1024 AVG x0 x1 th NOT NOT MIN MIN MIN MIN MIN MIN MAX MAX MAX 1 1 AVG AVG 195/256 x0 x1 th

  17. Two-bit Counter Circuit 1 7217/8192 AVG x0 x1 th NOT NOT MIN MIN MIN MIN MIN MIN MAX MAX MAX 1 1 AVG AVG 28867/32768 x0 x1 th

  18. Serving Suggestions • The counter generalizes to n bits easily • The n-bit counter takes Θ(n2) gates, due to the size of the NOT gadgets • We now have our counter • We next investigate the power of Leapfrog circuits, using the counter… • First, we will need to make precise what we mean by “Leapfrog circuits” carry-in xi NOT NOT MIN MIN MIN carry-out MAX xi

  19. Definition: LEAPFROG • Let LEAPFROG be the following problem: Given a circuit C and designated gates i and th, consider the sequence of vectors v1, v2, … obtained during gate-by-gate update of C from 0 in the order of the gate indices of C:“Is there an index t such that vti> vtth?” • LEAPFROG captures our notion of what Leapfrog circuits “compute”

  20. 1 MAX input AVG LEAPFROG vs. STABLE CIRCUIT • NB: Not the same problem!! • But, STABLE CIRCUIT obviously reduces to a special case of LEAPFROG (include a gate that outputs constant 1/2-1/22|C|…) • Is LEAPFROG hard? • YES -- we will see in a moment • Does LEAPFROG reduce to STABLE CIRCUIT? • If “yes,” then STABLE CIRCUIT is also hard. • Notice the gadget: if its input is ever above threshold, a wire in the gadget stays above threshold • Still,this doesnot show LEAPFROG reduces to STABLE CIRCUIT… (the internal wire must also pass through the NOT gadgets)

  21. NOT NOT MAX MAX MAX MAX MIN LEAPFROG is hard! (NP-hard) Let any boolean formula be given… Ex: (x1~x2x3)  (~x1~x2x3) Since we have AND, OR, and NOT gates, formulas easily translate into circuits. x1 x2 x3 th, etc. If we attach xi to the ith bit of the counter, we try all possible assignments, allowing us to reduce SAT to LEAPFROG. The number of gates in these SAT circuits is quadratic in the length of the formula. (x1~x2x3)(~x1~x2x3)

  22. LEAPFROG is really hard! (PSPACE-hard) x1 • We can still do better: using the counter, we will decide whether quantified boolean formulas are valid (Reducing TQBF to LEAPFROG) • Assume WLOG that the quantifiers alternate: odd variables are universal, even ones are existential • Observe that the counter “walks” along the leaves of a tree of assignments, left to right. • Suppose that at the bottom we evaluate the quantifier-free part of the formula on the specified assignment.  x0 x0  00 01 10 11 • Now suppose at every  level of the tree, we have one bit of memory for the left branch • Set it to T when the branch is T, reset it to F when leaving that subtree. • Pass T up the tree when • We see T at either branch at an  level • We see T at the right branch of a  level with the left branch bit already set to T. • T is passed up from the top of the tree iff we have a TQBF.

  23. Quantifier Circuit: xi(xi-1A) xi vi0 A Carry-out: xi • IH: the wire A will be T iff the shorter formula with alternating quantifiers, A, is satisfied by the assignment to xn,…,xi-1 from the counter • vi0 is our bit of memory storing the value of (A|xi = F) (the left branch) under the fixed assignment to xn,…,xi+1 • When there is a carry out of xi, xi+1 has altered, so we reset vi0 to F • If vi0 = (A|xi= F) = T and (A|xi = T) = T (on the right branch), then the wire labeled xixi-1A is T. Otherwise, the wire remains F. • Notice we try both settings of xi-1for each branch. The wire xi xi-1A is T iff xi xi-1A is satisfied by the assignment to xn,…,xi+1, so the Inductive Hypothesis is satisfied NOT MIN MIN MIN NOT MIN MIN MIN MIN MIN MIN MAX MAX MAX MIN MIN MIN xi vi0 xi xi-1A

  24. End of the Line: Thwarted by PSPACE • In the limit, the separation between T and F in our counter shrinks as the internal wires approach 1. • Recall: finding values in the limit (the minimum stable solution) is known to be in NPco-NP • Answers to PSPACE-hardproblems (TQBF) may be encoded on the wires as we update • Since circuits of AND/OR/NOT gates can be evaluated in PSPACE, we would need to drastically alter our model to solve anything harder • In the limit, it is impossible to distinguish the values in Leapfrog circuits unless NP = PSPACE • That is, unless NP = PSPACE, LEAPFROG does not reduce to STABLE CIRCUIT

  25. Stoppable NOT Gadget This gadget behaves identically to the regular NOT, unless check is set high, in which case, all outputs are set high. Gadgets such as this suggest that the problem with our Leapfrog counter was in the AVG gates we used to “power” it from 0. th check x1 x0 x2 AVG MAX MIN MIN MIN MIN MAX AVG MAX MAX MAX x1 x2 th check ~x0

  26. Open problems • How hard is STABLE CIRCUIT? • We had also succeeded in placing it in PLS, but still have no hardness results • Is STABLE CIRCUIT PLS-complete? • Is STABLE CIRCUIT in P? • How hard is LEAPFROG, actually? • Trivially RE, but this says rather little • Is LEAPFROG decidable?

More Related