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Multi-Cores: Architecture/VLSI Perspective. The Hardware-Software Relationship: Date or Dump?. Embedded Applications -- Spencer. From discreet cochlear implants to high-end biomedical imaging! Multi-cores speed up performance by 50x! Creating new application domains!.
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Multi-Cores: Architecture/VLSI Perspective The Hardware-Software Relationship: Date or Dump? University of Utah
Embedded Applications --Spencer • From discreet cochlear implants to high-end biomedical imaging! • Multi-cores speed up performance by 50x! • Creating new application domains!
How to use “multiple” cores? Parallel programming Synchronization Deadlock Livelock Memory management
How to use “multiple” cores? Oct 31st 2007 Program = Communication + Computation • Global restructuring and parallelization 4
Structured “Communication” Oct 31st 2007 Lang: StreamIt, MPI Compilers: RAW, CoGenE Architecture: TRIPS, HWRT • Key: Help other levels and leverage communication 5
Another Constraint? Hey.. Surprise!!! Parallel programming Synchronization Deadlock Livelock Memory management Communication Scheduling
Another Constraint? Oh God!!! Communication Scheduling
Focus of Architecture Research • Reduce the load of programmers • Hardware transactional memory • Aggressive pre-fetching • Dynamic reconfiguration at every possible level • Keep the architectural innovations transparent to compilers or programmers • Learn from the mistakes of ITANIUM ! • Remember the success of OOO execution
9 Reliability Issues --Niti • Shrinking transistor sizes & lower voltages • Increased transient faults, process variations – leakage power and frequency variations, hard errors, interconnect noise • Many-core – “Many cores”may not work reliably • Some cores will end up providing redundancy • Heterogeneous cores may be able to help • Simple in-order cores can provide redundancy at low cost • The compute power gain of many-core can get offset by reliability requirements of the system
On-Chip Sensor Networks --Nathaniel, Amlan Analog sensors everywhere! • Need to monitor power, voltage droop, variation, critical paths, delays, slew rates, etc. • Control system to react to changes. • In multi-core, sensor network will only grow. On-chip sensors Xeon and Itanium processors JSSC Jan 06 & 07