An adaptable FPGA-based System for Regular Expression Matching

1. An adaptable FPGA-based System for Regular Expression Matching Authors: Ivano Bonesana, Marco Paolieri, Marco D. Santambrogio Publisher: DATE (Design, Automation and Test in Europe) 2008 Present: Chung-Chan Wu Date:April 23 2008 Department of Computer Science and Information Engineering National Cheng Kung University, Taiwan R.O.C.

2. Outline • Introduction • ReCPU Framework Flow • ReCPU Instruction Structure • Architecture Description • Experimental Result

3. Introduction • RE：Regular Expression • We do not build either Deterministic nor Nondeterministic Finite Automaton of the RE • The architecture is optimized to execute computations in a parallel and pipelined way • VLIW design style (Very long instruction word) • We developed a compiler to translate REs into bitwise instructions.

4. ReCPU Framework Flow

5. Regular Expression

6. Compilation Phase • By modifying the number of clusters (parameters) in the ReCPU • Performance • Power • area • The compiler • written in Python • starting from the high level description of the RE • generates the files • be loaded in the instruction memory

7. ReCPU Instruction Structure • Operators like * and + correspond to loop instructions. • Nested parentheses (e.g. (((ab)*(c|d))|(abc))) are managed as function calls. • An open parenthesis inside an RE is a call instruction while the closed one is a return instruction.

8. Architecture Description • ReCPU uses two separate memories: • Data memory for the input text • instruction memory for the RE • In the Data Path are placed all the different parallel comparators organized in Clusters. • Cluster Width：The total number of elements in a cluster • The processor is composed of severalClusters - the total number is indicated as NCluster

9. Block Diagram of ReCPU (4 Clusters)

10. Comparator Cluster

11. Finite State Machine of the Control Unit

12. Experimental Result

13. Experimental Result