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Compact Architecture for High-Throughput Regular Expression Matching on FPGA

Compact Architecture for High-Throughput Regular Expression Matching on FPGA. Authors: Yi-Hua E. Yang, Weirong Jiang and Viktor K. Prasanna Publisher: ACM/IEEE Symposium on Architectures for Networking and Communication Systems (ANCS' 08) Present : Chen-Rong Chang Date: March , 18, 2009.

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Compact Architecture for High-Throughput Regular Expression Matching on FPGA

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  1. Compact Architecture for High-Throughput Regular Expression Matching on FPGA Authors: Yi-Hua E. Yang, Weirong Jiang and Viktor K. Prasanna Publisher:ACM/IEEE Symposium on Architectures for Networking and Communication Systems (ANCS' 08) Present:Chen-Rong Chang Date:March, 18, 2009 Department of Computer Science and Information Engineering National Cheng Kung University, Taiwan R.O.C.

  2. Outline • Basic Architecture on FPGA • From Regular Expression to NFA • From RE-NFA to HDL • Architectural Optimizations • Multi-Character Input Matching • Centralized Character Classification • Staging and Pipelining • Performance Comparison

  3. From Regular Expression to NFA(1/4)

  4. From Regular Expression to NFA(2/4)

  5. From Regular Expression to NFA(3/4)

  6. From Regular Expression to NFA(4/4)

  7. From RE-NFA to HDL EX: Input=bcbc#

  8. Architectural Optimizations • We apply three optimizations to improve our basic design: • (1) multi-character input matching • (2) centralized character classication • (3) staging and pipelining • While these concepts have been proposed in previous research the techniques used here are unique to our design and take advantage of the modularity of the proposed architecture.

  9. Multi-Character Input Matching EX: Input1=bcbc# Input2=bca# #

  10. Centralized Character Classification

  11. Staging and Pipelining

  12. Performance Comparison(1/4)

  13. Performance Comparison(2/4)

  14. Performance Comparison(3/4)

  15. Performance Comparison(4/4)

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