An Entropy-based Learning Hardware Organization Using FPGA

1. An Entropy-based Learning Hardware Organization Using FPGA Janusz Starzyk and Yongtao GuoMarch 19, 2001 FPGA Lab School of Electrical Engineering and Computer Science Ohio University, Athens, OH 45701, U.S.A.

2. Outline • Introduction • Entropy-based Evaluator • Hardware Implementation • Synthesis & Performance • Summary

3. Introduction • WHAT ARE NEURAL NETWORKS ? • Main function • Like human brain • FEATURES OF NEURAL NETWORKS ? • Self-Organizing Learning. • Fault tolerant. • Fast run but not fast to learn. • Particularly suited to problems. • Can be trained to generate non-linear mappings.

4. Introduction --Self Organizing Learning • Feed-forward (FF) • Threshold-controlled input (TCI) • Threshold-controlled outputs (TCO) • Entropy based evaluator • Information deficiency

5. Here, , , represent the probabilities of each class, attribute probability and joint probability respectively. Entropy-based Evaluator Entropy based information index

6. Entropy-based Evaluator Subspaces information deficiency

7. Entropy-based Evaluator - Information Index Necessary Approximation Mult(a,b)=E(Sub(L(a)+L(b),B)) multiplication Divd(a,b)=E(Sub(L(a),L(b))) division L(a) returns the location (starting from 0) of the most significant bit position of a, E(a) forces 1 on a-th bit position ( a modification of this operation forces 1 on a, a-2, a-4 etc. bit positions). B word length

8. Figure Structural Simulation Entropy-based Evaluator - Structural Simulation

9. Entropy-based Evaluator - VHDL Design

10. Fig. VHDL Simulation at RTL Entropy-based Evaluator - VHDL Simulation at RTL

11. LUT EBE Threshold Comparator Unit ECU OE MaxInfo Hardware Implementation EBE hardware model: • Memory circuit (LUT) • Comparator unit • ECU • Two registers

12. M R From LUT R DIV > To LUT > SHI N T R +/- MUL R To COM Threshold > R From LUT Threshold Adjustment Figure-Entropy Calculating Unit Hardware Implementation- ECU Architecture

13. Hardware Implementation Other components: • Control Unit System clock, state transfer signals, handshake signals. • MUX & DMUX Parallel process of the multi-feature data in the input classes. • Display Unit Real-time monitor for the data transfer. • EBE Interface Between FIFO control unit, PCI bus and EBE for rapid data transfer and easy online systemdebugging.

14. PCI Interface Core LUT EBE R1 Threshold Display R2 Comparator Unit ECU FIFO Ctrl EBE Interface PCI MUX DMUX OE MaxInfo Req Start Done SEL SEL Control Unit Hardware Implementation Output Figure- FPGA-based Architecture

15. Hardware Implementation Reconfigurable Advantage • Exploit cases where operation can be bound and then reused a large number of times. • Customization of operator type, width, and interconnect. • Flexible low overhead exploitation of application parallelism.

16. vvs Schematic Capture VHDL RTL Simulation Optimization Check Check .bit file Download Figure- Implementation Flow Synthesis & Performance -Implementation Flow

17. Synthesis & Performance --Map design to Virtex

18. Synthesis & Performance --FPGA Map

19. Synthesis & Performance --Schematic

20. Synthesis & Performance --FPGA Floorplan Vendor: Xilinx Family: VIRTEX Device: V800BG432 Speed: -4 Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 47 out of 316 14% Number of BLOCKRAMs 4 out of 28 14% Number of SLICEs 463 out of 9408 4 % Number of DLLs 1 out of 4 25% Number of GCLKs 1 out of 4 25% Number of TBUFs 256 out of 9632 2% Number of flip-flops: 336 Minimum period: 24.838ns Maximum frequency: 40.261MHz Total equivalent gate count for design: 88,186 Additional JTAG gate count for IOBs: 2,304

21. Summary • Self-Organizing Algorithm • Matlab & VHDL Simulation • Hardware Architecture • Synthesis • Analog Circuits