Minimum Systems and the PIC 16F84A

1. Minimum Systems and the PIC 16F84A Chapter Two Dr. Gheith Abandah

2. Outline • Review of Memory Technologies • The PIC 16 Series • PIC 16F84A • The PIC 16F84A Memory • The Oscillator • Instruction Cycle • Power-up and Reset Dr. Gheith Abandah

3. Review of Memory Technologies • Read Only Memory (ROM) • Random Access Memory (RAM): Read/Write • Static RAM (SRAM): Each cell is a simple flip-flop of six transistors, CMOS, volatile • Programmable ROM (PROM): Each cell is one transistor, MOS, non-volatile, plastic package. • Erasable PROM (EPROM): Each cell is one transistor, MOS, non-volatile, erasable with ultraviolet light, ceramic package with quartz window. Dr. Gheith Abandah

4. Review of Memory Technologies – cont. • Electrically EPROM (EEPROM): Each cell is one transistor with additional transistors for programming, MOS, non-volatile, erasable electrically (takes time), suffers from wear. • Flash Memory: Each cell is one transistor, MOS, non-volatile, erasable electrically (takes time) in blocks, suffers from wear, popular. Dr. Gheith Abandah

5. The PIC 16 Series Dr. Gheith Abandah

6. The PIC 16 Series Dr. Gheith Abandah

7. The PIC 16 Series Dr. Gheith Abandah

8. PIC 16F84A Dr. Gheith Abandah

9. PIC 16F84A Architecture Dr. Gheith Abandah

10. The 16F84A Status Register • C: Carry/Borrow’ • DC: Digit Carry/Borrow’ • Z: Zero • PD’: Power Down • TO’: Time Out • RP0: Register Bank Select • RP1, IRP: Not implemented Dr. Gheith Abandah

11. The 16F84A Memory Dr. Gheith Abandah

12. Program Memory and Stack Dr. Gheith Abandah

13. Configuration Word Allows the user to define certain configurable features of the microcontroller, at the time of program download. Dr. Gheith Abandah

14. Data memory and Special Function Registers FSR: File Select Register for indirect addressing. EEADR: EEPROM Address EEDATA: EEPROM Data EECON1: Control; RD, WREN, WR, EEIF EECON2: 55H to AAH Dr. Gheith Abandah

15. The Oscillator • It is necessary to provide the ‘clock’ signal. • The clock is a continuously running fixed frequency logic square wave. • The overall speed of the microcontroller operation is entirely dependent on this clock frequency. • Higher frequency -> Higher Performance and higher power consumption. Dr. Gheith Abandah

16. Instruction Cycle • The main oscillator signal is divided by 4 to produce the instruction cycle time. Dr. Gheith Abandah

17. Pipelining • All PIC microcontrollers implement pipelining. • Pipelining fails when one instruction changes the contents of the Program Counter. Dr. Gheith Abandah

18. Power-up and Reset • At power-up, the Program Counter is forced to zero and the SFRs are reset so that peripherals are initially in a safe and disabled state. • There is also a master clear input MCLR’. Dr. Gheith Abandah

19. Summary • The PIC 16 Series is a diverse and effective family of microcontrollers. • The 16F84A architecture is representative of all 16 Series microcontrollers, with Harvard structure, pipelining and a RISC instruction set. • The PIC 16F84A has a limited set of peripherals, chosen for small and low-cost applications. It is thus a smaller member of the family, with features that are a subset of any of the larger ones. • The 16F84A uses three distinct memory technologies for its different memory areas. • A particular type of memory location is the Special Function Register, which acts as the link between the CPU and the peripherals. • Reset mechanisms ensure that the CPU starts running when the appropriate operating conditions have been met, and can be used to restart the CPU in case of program failure. Dr. Gheith Abandah