PIC

1. PIC University of Belgrade School of Electrical Engineering Department of Computer Science Authors: Goran Timotic gogi@beotel.yu Gvozden Marinkovic mgvozden@eunet.yu Prof. Dr. Veljko Milutinovic vm@etf.bg.ac.yu

2. PIC - Introduction • Microchip is the Embedded Control Solutions Company • The company’s focus is on products that meet the needs of the embedded control market • Some of the benefits for the customer include: • Quick time to market • Allows code changes to product, during production run • No Non-Recurring Engineering (NRE) charges for Mask Revisions • Ability to easily serialize the product • Ability to store calibration data, without additional hardware • Better able to maximize PICmicro MCU inventory • Less risk, since the same device is used for development as well as for production.

3. PIC - Introduction • PICmicro devices are grouped by the size of their Instruction Word • The three current PICmicro families are: • Base-Line: 12-bit Instruction Word length • Mid-Range: 14-bit Instruction Word length • High-End: 16-bit Instruction Word length

4. PIC - Introduction • PIC12C5XX Family - 8-Pin, 8-Bit CMOS Microcontrollers • PIC12CE5XX Family - 8-Pin, 8-Bit CMOS Microcontrollers with EEPROM Data Memory • PIC12C67X Family - 8-Pin, 8-Bit CMOS Microcontrollers with A/D Converter • PIC12CE67X Family - 8-Pin, 8-Bit CMOS Microcontrollers with A/D Converter and EEPROM Data Memory PIC12 Family

5. PIC - Introduction • PIC16C5X Family & PIC16HV540 - EPROM/ROM-Based 8-Bit CMOS Microcontroller Series • PIC16C55X Family EPROM-Based 8-Bit CMOS Microcontrollers • PIC16C6X Family 8-Bit CMOS Microcontrollers • PIC16X62X Family 18-Pin EPROM-Based 8-Bit CMOS Microcontrollers • PIC16CE62X Family 8-Bit CMOS Microcontrollers with Analog Comparators and EEPROM Data Memory • PIC16C7X Family 8-Bit CMOS Microcontrollers with A/D Converter • PIC16C7XX Family 8-Bit CMOS Microcontrollers with A/D Converter for USB, PS/2 and Serial Device Applications • PIC16C9XX Family 8-Bit CMOS Microcontrollers with LCD Driver PIC16 Family

6. PIC - Introduction • PIC17C4X Family - High-Performance 8-Bit CMOS EPROM/ROM Microcontrollers • PIC17C7XX Family - High-Performance 8-Bit CMOS EPROM Microcontrollers PIC17 Family

7. PIC - Introduction • The high performance of the PICmicro™ devices can be attributed to a number of architectural features commonly found in RISC microprocessors: • Harvard architecture • Long Word Instructions • Single Word Instructions • Single Cycle Instructions • Instruction Pipelining • Reduced Instruction Set • Register File Architecture • Orthogonal (Symmetric) Instructions

8. PIC - Architecture Overview

9. PIC - Oscillator • The internal oscillator circuit is used to generate the device clock • Four device clock periods generate one internal instruction clock (TCY) cycle • There are up to eight different modes, which the oscillator may have: • LP Low Frequency (Power) Crystal • XT Crystal/Resonator • HS High Speed Crystal/Resonator • RC External Resistor/Capacitor (same as EXTRC with CLKOUT) • EXTRC External Resistor/Capacitor • EXTRC External Resistor/Capacitor with CLKOUT • INTRC Internal 4 MHz Resistor/Capacitor • INTRC Internal 4 MHz Resistor/Capacitor with CLKOUT

10. PIC - Reset • The reset logic is used to place the device into a known state • The source of the reset can be determined by using the device status bits • Most registers are unaffected by a reset, their status is unknown on POR and unchanged by all other resets • The other registers are forced to a “reset state” on Power-on Reset, MCLR, WDT reset, Brown-out Reset, Parity Error Reset, and on MCLR reset during SLEEP • While the PICmicro™ is in a reset state, the internal phase clock is held at Q1 (beginning of an instruction cycle)

11. PIC - Reset 2 • Devices differentiate between various kinds of reset: • Power-on Reset (POR) - pulse is generated on-chip when VDD rise is detected • MCLR reset during normal operation • MCLR reset during SLEEP • WDT reset during normal operation • Brown-out Reset (BOR) - places the device into reset when the device voltage falls below a trip point (BVDD) • Parity Error Reset (PER)

12. PIC - Instruction Flow/Pipelining • An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3, and Q4) • Fetch takes one instruction cycle while decode and execute takes another instruction cycle • Due to Pipelining, each instruction effectively executes in one cycle • If an instruction causes the program counter to change (e.g. GOTO) then an extra cycle is required to complete the instruction

13. PIC - Instruction Pipeline Flow

14. PIC - Central Processing Unit (CPU) • CPU is responsible for: • fetching the correct instruction for execution • decoding that instruction • executing that instruction • Sometimes works in conjunction with the ALU to complete the execution of the instruction (in arithmetic and logical operations) • The CPU controls the program memory address bus, the data memory address bus, and accesses to the stack

15. PIC - Instruction Clock • Each instruction cycle (TCY) is comprised of four Q cycles (Q1-Q4) • The Q cycles provide the timing/designation for the Decode, Read, Process Data, Write, etc., of each instruction cycle • The four Q cycles that make up an instruction cycle (TCY) can be generalized as: • Q1: Instruction Decode Cycle or forced No operation • Q2: Instruction Read Data Cycle or No operation • Q3: Process the Data • Q4: Instruction Write Data Cycle or No operation

16. PIC - Arithmetic Logical Unit (ALU) • PICmicro MCUs contain an 8-bit ALU and an 8-bit working register • The ALU is a general purpose arithmetic and logical unit • ALU performs arithmetic and Boolean functions between the data in the working register and any register file • The ALU is 8-bits wide and is capable of addition, subtraction, shift and logical operations • In two-operand instructions • one operand is the working register (W register) • the other operand is a file register or an immediate constant • In single operand instructions, • the operand is either the W register or a file register

17. PIC - STATUS Register • IRP: Register Bank Select bit (used for indirect addressing) • RP1:RP0: Register Bank Select bits (used for direct addressing) • TO: Time-out bit • PD: Power-down bit • Z: Zero bit • DC: Digit carry/borrow bit • C: Carry/borrow bit • The STATUS register contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory

18. PIC - OPTION_REG Register • Readable and writable register which contains various control bits to configure the TMR0/WDT prescaler, the external INT Interrupt, TMR0, and the weak pull-ups on PORTB • RBPU: PORTB Pull-up Enable bit • INTEDG: Interrupt Edge Select bit • T0CS: TMR0 Clock Source Select bit • T0SE: TMR0 Source Edge Select bit • PSA: Prescaler Assignment bit • PS2:PS0: Prescaler Rate Select bits

19. PIC - PCON Register • The Power Control (PCON) register contains flag bit(s), that together with the TO and PD bits, allows the user to differentiate between the device resets • MPEEN: Memory Parity Error Circuitry Status bit • PER: Memory Parity Error Reset Status bit • POR: Power-on Reset Status bit • BOR: Brown-out Reset Status bit

20. PIC - Memory Organization • There are two memory blocks • Program memory • Data memory • Each block has its own bus, so that access to each block can occur during the same oscillator cycle • The data memory can further be broken down into General Purpose RAM and the Special Func-tion Registers (SFRs)

21. PIC - Program Memory Organization

22. PIC - Program Memory Organization • Mid-Range MCU devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space • The width of the program memory bus (instruction word) is 14-bits • Since all instructions are a single word, a device with an 8K x 14 program memory has space for 8K of instructions • This program memory space is divided into four pages of 2K words each • To jump between the program memory pages, the high bits of the Program Counter (PC) must be modified. This is done by writing the desired value into a SFR called PCLATH (ProgramCounter Latch High)

23. PIC - Program Memory Organization • Reset Vector - on any device, a reset forces the Program Counter (PC) to address 0h • Interrupt Vector - when an interrupt is acknowledged the PC is forced to address 0004h • Calibration Information - some devices have calibration information stored in their program memory. This information is programmed by Microchip when the device is under final test • Computed GOTO - accomplished by adding an offset to the program counter (ADDWF PCL)

24. PIC - Program Memory Organization • Program Counter (PC) - specifies the address of the instruction to fetch for execution • The low byte is called the PCL register. This register is readable and writable • The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register • Stack - 8-level deep x 13-bit wide hardware stack • allows a combination of up to 8 program calls and interrupts to occur • contains the return address from this branch in program execution

25. PIC - Program Memory Organization • Program Memory Paging

26. PIC - Data Memory Organization • Data memory is made up of the Special Function Registers (SFR) area, and the General Purpose Registers (GPR) area • General Purpose Registers (GPR) • GPRs are the general area for data storage and scratch pad operations • We refer to this area as the Common RAM • Special Function Registers (SFR) • The SFRs are used by the CPU and Peripheral Modules for controlling the desired operation of the device. • These registers are implemented as static RAM

27. PIC - Data EEPROM • The EEPROM data memory is readable and writable during normal operation (full VDD range) • A byte write automatically erases the location and writes the new data (erase before write) • This memory is not directly mapped in the register file space • It is indirectly addressed through the Special Function Registers • There are four SFRs used to read and write this memory • EECON1 • EECON2 (not a physically implemented register) • EEDATA - holds the 8-bit data for read/write • EEADR - holds the address of the EEPROM location being accessed

28. PIC - Interrupts • One interrupt source for each peripheral module • Some modules may generate multiple interrupts (such as the USART module) • There is a minimum of one register used in the control and status of the interrupts (INTCON) • If the device has peripheral interrupts, then it will have registers to enable the peripheral interrupts and registers to hold the interrupt flag bits. Depending on the device, the registers are: • PIE1 • PIR1 • PIE2 • PIR2

29. PIC - Interrupts • The current interrupts are: • INT Pin Interrupt (external interrupt) • TMR0 Overflow Interrupt • PORTB Change Interrupt (pins RB7:RB4) • Comparator Change Interrupt • Parallel Slave Port Interrupt • USART Interrupts • Receive Interrupt • Transmit Interrupt • A/D Conversion Complete Interrupt • LCD Interrupt. • Data EEPROM Write Complete Interrupt • Timer1 Overflow Interrupt • Timer2 Overflow Interrupt • CCP Interrupt • SSP Interrupt

30. PIC - Interrupts • Control Registers • INTCON Register • PIE Register(s) • PIR Register(s)

31. PIC - Interrupts • INTCON Register - readable and writable register, which contains various enable and flag bits • GIE: Global Interrupt Enable bit • PEIE: Peripheral Interrupt Enable bit • T0IE: TMR0 Overflow Interrupt Enable bit • INTE: INT External Interrupt Enable bit • RBIE: RB Port Change Interrupt Enable bit • T0IF: TMR0 Overflow Interrupt Flag bit • INTF: INT External Interrupt Flag bit • RBIF: RB Port Change Interrupt Flag bit

32. PIC - Interrupts • PIE Register(s) - Peripheral Interrupt Enable register(s) (the number of PIE registers depends on the number of peripheral interrupt sources) • TMR1IE: TMR1 Overflow Interrupt Enable bit • TMR2IE: TMR2 to PR2 Match Interrupt Enable bit • CCP1IE: CCP1 Interrupt Enable bit • CCP2IE: CCP2 Interrupt Enable bit • SSPIE: Synchronous Serial Port Interrupt Enable bit

33. PIC - Interrupts • RCIE: USART Receive Interrupt Enable bit • TXIE: USART Transmit Interrupt Enable bit • ADIE: A/D Converter Interrupt Enable bit • ADCIE: Slope A/D Converter comparator Trip Interrupt Enable bit • OVFIE: Slope A/D TMR Overflow Interrupt Enable bit • PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit • EEIE: EE Write Complete Interrupt Enable bit • LCDIE: LCD Interrupt Enable bit • CMIE: Comparator Interrupt Enable bit

34. PIC - Interrupts • PIR Register(s) - Peripheral Interrupt Flag registers contain the individual flag bits for the peripheral interrupts • TMR1IF: TMR1 Overflow Interrupt Flag bit • TMR2IF: TMR2 to PR2 Match Interrupt Flag bit • CCP1IF: CCP1 Interrupt Flag bit • CCP2IF: CCP2 Interrupt Flag bit • SSPIF: Synchronous Serial Port Interrupt Flag bit • RCIF: USART Receive Interrupt Flag bit • TXIF: USART Transmit Interrupt Flag bit

35. PIC - Interrupts • ADIF: A/D Converter Interrupt Flag bit • ADCIF: Slope A/D Converter Comparator Trip Interrupt Flag bit • OVFIF: Slope A/D TMR Overflow Interrupt Flag bit • PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit • EEIF: EE Write Complete Interrupt Flag bit • LCDIF: LCD Interrupt Flag bit • CMIF: Comparator Interrupt Flag bit

36. PIC - Interrupts • Interrupt Latency • Interrupt latency is defined as the time from the interrupt event (the interrupt flag bit gets set) to the time that the instruction at address 0004h starts execution (when that interrupt is enabled) • For synchronous interrupts (typically internal), the latency is 3TCY • For asynchronous interrupts (typically external), the interrupt latency will be 3 - 3.75TCY • Context Saving During Interrupts • During an interrupt, only the return PC value is saved on the stack • Typically, users may wish to save key registers during an interrupt e.g. W register and STATUS register. This has to be implemented in software

37. PIC - I/O • General purpose I/O pins can be considered the simplest of peripherals • They allow the PICmicro™ to monitor and control other devices • To add flexibility and functionality to a device, some pins are multiplexed with an alternate function(s)

38. PIC - I/O Descriptions

39. PIC - I/O Descriptions

40. PIC - I/O Descriptions

41. PIC - Parallel Slave Port (PSP) • Some devices have an 8-bit wide Parallel Slave Port (PSP) • This port is multiplexed onto one of the devices I/O ports • The PORT operates as an 8-bit wide Parallel Slave Port, or microprocessor port, when the PSPMODE control bit is set (in this mode, the input buffers are TTL)

42. PIC - Timer0 • The Timer0 module has the following features: • 8-bit timer/counter • Readable and writable • 8-bit software programmable prescaler • Clock source selectable to be external or internal • Interrupt on overflow from FFh to 00h • Edge select for external clock

43. PIC - Timer1 • The Timer1 module is a 16-bit timer/counter • It consists of two 8-bit registers (TMR1H and TMR1L), which are readable and writable • Timer1 can operate in one of three modes: • As a synchronous timer • As a synchronous counter • As an asynchronous counter

44. PIC - Timer2 • Timer2 is an 8-bit timer with • Prescaler • Postscaler • Period register • Using the prescaler and postscaler at their maximum settings, the overflow time is the same as a 16-bit timer

45. PIC - Capture/Compare/PWM • Each CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate in three modes: • As a 16-bit capture register • As a 16-bit compare register • As a 10-bit PWM master/slave Duty Cycle register • The CCP modules are identical in operation, with the exception of the operation of the special event trigger

46. PIC - Synchronous Serial Port (SSP) • The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripherals or microcontroller devices • These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. • The SSP module can operate in one of two modes: • Serial Peripheral Interface (SPI™) • Inter-Integrated Circuit (I2C™) • Slave mode • I/O slope control, and Start and Stop bit detection to ease software implementation of Master and Multi-master modes

47. PIC - Synchronous Serial Port (SSP) • Serial Peripheral Interface (SPI™) • Allows 8-bits of data to be synchronously transmitted and received simultaneously • All four modes of SPI are supported, as well as Microwire™ (sample edge) when the SPI is in the master mode • To accomplish communication, typically three pins are used: • Serial Data Out (SDO) • Serial Data In (SDI) • Serial Clock (SCK)

48. PIC - Synchronous Serial Port (SSP) • Inter-Integrated Circuit (I2C™) • The SSP module in I2C mode fully implements all slave functions, except general call support • Provides interrupts on start and stop bits in hardware to facilitate software implementations of the master functions • Implements the standard mode specifications as well as 7-bit and 10-bit addressing

49. PIC - USART • The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules (other is the SSP module) • The USART can be configured in the following modes: • Asynchronous (full duplex) • CRT terminals • personal computers • Synchronous - Master (half duplex) • A/D or D/A integrated circuits • Serial EEPROMs etc. • Synchronous - Slave (half duplex)

50. PIC - A/D Converter • The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number • The output of the sample and hold is the input into the converter, which generates the result via successive approximation • The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode • The A/D module has three registers: • A/D Result Register (ADRES) • A/D Control Register0 (ADCON0) - controls the operation of the A/D module • A/D Control Register1 (ADCON1) - configures the functions of the port pins