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SRAM Design for Yield Optimization at Reduced Voltages Near Threshold

Jennifer Winikus Computer Engineering Seminar Michigan Technological University February 10,2011. SRAM Design for Yield Optimization at Reduced Voltages Near Threshold. Presentation based on :. Yield-Driven Near- Theshold SRAM Desing.

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SRAM Design for Yield Optimization at Reduced Voltages Near Threshold

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  1. Jennifer Winikus Computer Engineering Seminar Michigan Technological University February 10,2011 SRAM Design for Yield Optimization at Reduced Voltages Near Threshold J Winikus EE5900

  2. Presentation based on : Yield-Driven Near-Theshold SRAM Desing Gregory Chen, Dennis Sylvester, David Blaauw, and Trevor Mudge IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Vol. 18 No. 11, November 2010 J Winikus EE5900

  3. Overview • SRAM Performance Background • SRAM 6T and 8T designs • Experiment Methodology • Experimental Results • Conclusions J Winikus EE5900

  4. Introduction • Reduction in energy consumption is a high priority objective for electronics • RAM cells are optimized by utilizing transistors instead of flip flops to improve density • Transistors have increase in “failure” as VDD is minimized near and below VTH • Simulations of 8T and 6T SRAM at various sizes, VDD, VTH performed to analyze for future applications J Winikus EE5900

  5. RAM • RAM is the acronym for Random Access Memory • Utilized by computers and digital devices as a temporary memory storage to store data as it is processed • RAM and Processor speeds are the main components in the speed of a computer except for saving functions that the hard drive capabilities factor in J Winikus EE5900

  6. SRAM • Acronym for Static Random Access Memory • Denser then flip flops • Faster then DRAM • Holds the data as long as power is applied • Form arrays on the RAM chips J Winikus EE5900

  7. Power Regions in Transistors • Three power regions exist for Transistors: triode, saturation and cut-off • Near Threshold region is classified as between 400 and 700 mV Power Regions in MOSFET http://en.wikipedia.org/wiki/File:IvsV_mosfet.png J Winikus EE5900

  8. Random Dopant Fluctuation • The shifting of VTH for each transistor independently • Reduces Static Noise Margin • Causes mismatches within cells • More predominate influence on system at smaller VDD • Robustness is reduced with Random Dopant Fluctuation Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  9. Researchers at MIT have established that in general the relationship between total energy, energy leakage and Voltage in terms of the energy per ALU cycle • ALU cycles are computer architecture’s actions • ALU’s include read and write Advances in Ultra-Low-Voltage Design Joyce Kwong, Anantha P. Chandrakasan, Massachusetts Institute of Technology J Winikus EE5900

  10. SRAM Designs • Designs are based around desired read and write speeds and stability • Cross coupled invertors are responsible for holding the state J Winikus EE5900

  11. Threshold Voltage • The voltage threshold in the MOSFET in which below the threshold the transistor is essentially off, only leakage current passes between the drain and source J Winikus EE5900

  12. Differential 6T Bit Cell • Read is performed by prechargin the cell and floating the bitline • Write is performed by driving opposite values to the bitline overriding the wordline Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  13. Failure Modes in 6T Cells • Read Upset • The voltage applied to the node holding the zero value is flipped due to noise • Dependent on the pass gate strength • Write • Timing • Hold • Static Noise Margin over powers the cross-coupled invertors causing the state being stored to flip J Winikus EE5900

  14. 8T Bit Cell SRAM • Useful for independent read-write ports, done by having adding two additional stacked negative channel FETS to the 6 cell to isolate the read and write ports from each other Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  15. 8T Failure • The addition of a separate Read Bitline eliminates the read failure that occurs in the 6T cell • Benefit of having the separate ports is that the remaining 6 transistors can be sized and doped to get the desired write stability • Failure mechanisms are otherwise the same as the 6T J Winikus EE5900

  16. Assist Circuit • An alternative to sizing modification • The premise is the modification of voltage thresholds for behaviors such that failures are prevented • In a duel port structure the word line voltage can be reduced when read process is performed • The implementation is done through addition of diodes • More complex drivers and decoding is needed with this methodology J Winikus EE5900

  17. Threshold Voltage Tuning • Modification of the threshold voltage of the transistors for the design specific goals • In application the tuning of MOSFETs are done by exciting dopants in the drain and source with laser pulses to achieve desired threshold voltages J Winikus EE5900

  18. Experimental Sizing and Doping • 8T SRAM is typically 33% larger then a 6T cell • VTH is optimized separately for the SRAM and the Logic to improve robustness and performance • Sizing alterations can be minimized by utilizing Assist Circuits J Winikus EE5900

  19. Experiment Design Methodology • The experiment methodology is an incremental conditioning structure • Only Word Line Drivers, Bit Line Drivers and bit cells are considered Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  20. Sampling • Monte Carlo • To account for high yeild systems like 8-kb SRAM with a 99% yeild, the failure rate is on the order of 10-7, which requires atleast 10 million simulations • SRAM with caches larger then 8-kb have smaller failure rates in which more simulations would be needed • Definition: Monte Carlo is the art of approximating an expectation by the sample mean of a function of simulated random variables(UC Berkley) • Importance Sampling • A unique probability density function is chosen for each transistor • Choosing a relative range to choose the samples from J Winikus EE5900

  21. Utilizing the Importance Sampling • Based on the percent error seen over many iterations, using the importance sampling 20,000 samples is sufficient for accurate results • Monte Carlo sampling would require 1012 samples for accurate results Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  22. The selected threshold voltages are chosen by choosing random values from within the sample probability distribution in which the normal distribution is shifted to induce a higher probability of failure • Selectively choosing the region speeds up analysis by eliminating samples from regions that are not of interest of the experiment Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  23. Robustness Caculation • Measured using Static Noise Margin or Corner Cases • Determines if optimization is complete J Winikus EE5900

  24. Equations for Importance Sampling for Robustness Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  25. Factors for Interpreting Results • Activity Factor is the average fraction of bit cells accessed per cycle • Vmin is the voltage in which the energy needed per operation is minimized J Winikus EE5900

  26. Experimental Results • Robustness is controlled to be constant through the modification of the size of the Bit Cells. • This allows for VTH tuning Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  27. Cache Classifications • L1- small in size, high in activity, total energy is mostly dynamic • L2- larger in size then L1, lower activity J Winikus EE5900

  28. The Effect of Tuning The energy reduction capability by tuning is most significantly seen in the 8T, a 61% reduction, including sizing as well results in an 83% energy reduction for the 8T cell Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  29. The activity behavior of the circuit is a substantial controlling factor in Vmin and Emin Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  30. The relationship produced between activity factor and Vmin demonstrates that the less activity the higher the Vmin Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  31. Of the components that assist circuit has been applied the only is beneficial in the sub threshold region for the overdriven word line Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  32. Performance is compromised with voltage reduction, but is minimized with the use of assists Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  33. The parabolic response of the energy cost per bit access for the write line displays the correspondence with the Vmin as below the approximate value the energy increases again • Below about 650 mV assist drooping is no longer considered to assist the circuit • Leakage increases in a near exponential behavior below Vmin Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  34. Assist circuit design benefits in this result for minimum voltage capabilities • Energy cost increases with activity Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. J Winikus EE5900

  35. Conclusions • With low failure rates, Importance Sampling is more efficient then Monte Carlo Sampling • Scaling to 300mV for 8T cells achieves 83% energy reduction • In effort to reduce power and maintain function-ability size is the compromise or through the addition of assist circuit • Assist modification of certain functional components is beneficial in failure prevention as voltage decreases J Winikus EE5900

  36. Relivance for Technology Progression • In the computer based 21st Century there is the drive for faster computing, smaller devices and less power consumption • The results display that at this point tuning threshold voltages is the most promising advancement to forward the consumer desires • The results express the trade off that exists, size or power, speed or power J Winikus EE5900

  37. Works Cited • Chen, Gregory, et al. "Yield-Driven Near-Threshold SRAM Design." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 18.11 (2010): 1590-1598. • R.P. Lu, A.D. Ramirez, B.W. Offord, and S.D. Russell of SPAWAR Systems Center Pacific for the Office of Naval Research.“Threshold Voltage Tuning of Metal-Gate MOSFETs Using an Excimer Laser”. http://www.techbriefs.com/component/content/article/8013 • Advances in Ultra-Low-Voltage Design .Joyce Kwong, Anantha P. Chandrakasan, Massachusetts Institute of Technology. http://www.ieee.org/portal/site/sscs/menuitem.f07ee9e3b2a01d06bb9305765bac26c8/index.jsp?&pName=sscs_level1_article&path=sscs/08Fall&file=Kwong.xml&xsl=article.xsl • Eric C. Anderson, 1999, UC Berkeley. “Lecture Notes for Stat 578C” http://ib.berkeley.edu/labs/slatkin/eriq/classes/guest_lect/mc_lecture_notes.pdf J Winikus EE5900

  38. Questions? J Winikus EE5900

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