1 / 10

Area-performance tradeoffs in sub-threshold SRAM designs

Area-performance tradeoffs in sub-threshold SRAM designs. George Cramer Ping-Chen Huang. Motivation. Consumer applications require low power and small memory design Implementing SRAM in subthreshold needs read/write assist circuits to maintain stability

jalia
Download Presentation

Area-performance tradeoffs in sub-threshold SRAM designs

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Area-performance tradeoffs in sub-threshold SRAM designs George Cramer Ping-Chen Huang

  2. Motivation • Consumer applications require low power and small memory design • Implementing SRAM in subthreshold needs read/write assist circuits to maintain stability Area trades off with stability and power

  3. Project Outlines • Investigate the area-performance trade-offs of 3 subthreshold SRAM designs • Four metrics: stability, delay, power, area • Fixed stability as the only constraint • Determine the most area-efficient subthreshold SRAM design as Vdd scales down

  4. Subthreshold SRAM designs N. Verma and A. P. Chandrakasan, “A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy,”IEEE Journal of Solid-State Circuits, vol. 43, no. 1, Jan. 2008, pp. 141-149. B. H. Calhoun and A. P. Chandrakasan, "A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation," IEEE Journal of Solid-State Circuits, vol. 42, no. 3, Mar. 2007, pp. 680-688.

  5. Modeling of SRAM Stability (a) Hold stress (b) Read stress (c) Write stress VQ low: M2 is off VQ low: M2 is off VQ low: M1 is off VQ high: M2 is off VQ high: M3 is off VQ high: VQB = 0

  6. Modeling of SRAM Delay Hold margin case: -> SNMhold= -0.0347+0.5*VDD Read margin case: Write margin case:

  7. Noise Margin Modeling Results Desired Read Margin = 80mV Desired Write Margin = 150mV

  8. Modeling of Delay and Power • Delay • Power • EOP Assume α=1

  9. SRAM Performance • 6T design has smallest read delay for its smallest equivalent • resistance from internal node to bitline • 10T design has smallest EOP

  10. Area-EOP Trade-off

More Related