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Multiplexers. Lecture L6.6v Section 6.2. Multiplexers. A Digital Switch A 2-to-1 MUX A 4-to-1 MUX A Quad 2-to-1 MUX The Verilog if…else Statement TTL Multiplexer. 4 x 1. MUX. s1. s0. Y. 0 0 C0 0 1 C1 1 0 C2 1 1 C3. Multiplexers. C0. C1. Y. C2. C3. s1. s0.
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Multiplexers Lecture L6.6v Section 6.2
Multiplexers • A Digital Switch • A 2-to-1 MUX • A 4-to-1 MUX • A Quad 2-to-1 MUX • The Verilog if…else Statement • TTL Multiplexer
4 x 1 MUX s1 s0 Y 0 0 C0 0 1 C1 1 0 C2 1 1 C3 Multiplexers C0 C1 Y C2 C3 s1 s0
4 x 1 MUX Multiplexers s1 s0 Y C0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 C1 Y C2 C3 s1 s0 A multiplexer is a digital switch 0 0
4 x 1 MUX Multiplexers s1 s0 Y C0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 C1 Y C2 C3 s1 s0 0 1
4 x 1 MUX Multiplexers s1 s0 Y C0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 C1 Y C2 C3 s1 s0 1 0
4 x 1 MUX Multiplexers s1 s0 Y C0 0 0 C0 0 1 C1 1 0 C2 1 1 C3 C1 Y C2 C3 s1 s0 1 1
A 2 x 1 MUX Z = A & ~s0 | B & s0
A 4 x 1 MUX A = ~s0 & C0 | s0 & C1 B = ~s0 & C2 | s0 & C3 Z = ~s1 & A | s1 & B Z = ~s1 & (~s0 & C0 | s0 & C1) | s1 & (~s0 & C2 | s0 & C3)
A 4 x 1 MUX Z = ~s1 & (~s0 & C0 | s0 & C1) | s1 & (~s0 & C2 | s0 & C3) Z = ~s1 & ~s0 & C0 | ~s1 & s0 & C1 | s1 & ~s0 & C2 | s1 & s0 & C3
s Y 0 A 1 B ProblemHow would you make aQuad 2-to-1 MUX? Quad 2-to-1 MUX [A3..A0] [Y3..Y0] [B3..B0] s
mux.v module mux24(A,B,s,Y); input [3:0] A; input [3:0] B; input s; output [3:0] Y; wire [3:0] Y; assign Y = {4{~s}} & A | {4{s}} & B; endmodule Quad 2-to-1 MUX [A3..A0] [Y3..Y0] [B3..B0] s
mux.v module mux24(A,B,s,Y); input [3:0] A; input [3:0] B; input s; output [3:0] Y; wire [3:0] Y; always @(A,B,s) if(s == 0) Y = A; else Y = B; endmodule Quad 2-to-1 MUX [A3..A0] [Y3..Y0] [B3..B0] s
1 16 1G Vcc 2 15 B 2G 3 14 1C3 A 4 13 1C2 2C3 5 12 1C1 2C2 6 11 1C0 2C1 7 10 1Y 2C0 8 9 GND 2Y 74LS153 TTL Multiplexer B A C0 C1 C2 C3 G Y X X X X X X 1 0 0 0 0 X X X 0 0 0 0 1 X X X 0 1 0 1 X 0 X X 0 0 0 1 X 1 X X 0 1 1 0 X X 0 X 0 0 1 0 X X 1 X 0 1 1 1 X X X 0 0 0 1 1 X X X 1 0 1 Dual 4-to-1-line multiplexer