Multiplexers

1. Multiplexers Section 3-7 Mano & Kime

2. Multiplexers & Demultiplexers • Multiplexers (Selectors) • Lab 1 – Behavioral VHDL -- Multiplexers • MUX as a Universal Element

3. 4– to– 1- Line Multiplexer

4. 4–to–1-Line Multiplexer with Transmission Gates

5. Quadruple 2–to–1-Line Multiplexer

7. Typical uses

8. Multiplexers • Multiplexers (Selectors) • Lab 1 – Behavioral VHDL -- Multiplexers • MUX as a Universal Element

9. Combinational Circuit Example n-line 2-to-1 Multiplexer n-line 2 x 1 MUX a(n-1:0) y(n-1:0) b(n-1:0) sel y 0 a 1 b sel

10. a(n-1:0) n-line 2 x 1 y(n-1:0) MUX b(n-1:0) sel An n-line 2 x 1 MUX library IEEE; use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g;

11. generic statement defines width of bus Entity Each entity must begin with these library and use statements library IEEE; use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g; port statement defines inputs and outputs

12. Entity Mode: in or out library IEEE; use IEEE.std_logic_1164.all; entity mux2g is generic (width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) ); end mux2g; Data type: STD_LOGIC, STD_LOGIC_VECTOR(width-1 downto 0);

13. Standard Logic library IEEE; use IEEE.std_logic_1164.all; type std_ulogic is ( ‘U’, -- Uninitialized ‘X’ -- Forcing unknown ‘0’ -- Forcing zero ‘1’ -- Forcing one ‘Z’ -- High impedance ‘W’ -- Weak unknown ‘L’ -- Weak zero ‘H’ -- Weak one ‘-’); -- Don’t care

14. Standard Logic Type std_ulogic is unresolved. Resolved signals provide a mechanism for handling the problem of multiple output signals connected to one signal. subtype std_logic is resolved std_ulogic;

15. a(n-1:0) n-line 2 x 1 y(n-1:0) MUX b(n-1:0) sel Architecture architecture mux2g_arch of mux2g is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; endif; end process mux2_1; end mux2g_arch; Note: <= is signal assignment

16. Architecture entity name process sensitivity list architecture mux2g_arch of mux2g is begin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; endif; end process mux2_1; end mux2g_arch; Sequential statements (if…then…else) must be in a process Note begin…end in process Note begin…end in architecture

17. Digilab2 – DIO1 Boards Pushbutton bn Spartan II FPGA Four 7-segment displays 8 LEDs LD 8 Switches SW 4 Pushbuttons BTN 74HC373 latch ldg <= ‘1’

18. Top-level Design – Lab 1

19. library IEEE; use IEEE.std_logic_1164.all; entity lab1 is port ( SW: in STD_LOGIC_VECTOR (1 to 8); BTN4: in STD_LOGIC; ldg: out STD_LOGIC; LD: out STD_LOGIC_VECTOR (1 to 4) ); end lab1;

20. architecture lab1_arch of lab1 is component mux2g generic(width:positive); port ( a: in STD_LOGIC_VECTOR (width-1 downto 0); b: in STD_LOGIC_VECTOR (width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR (width-1 downto 0) ); end component; constant bus_width: positive := 4; begin ldg <= '1'; -- enable 74HC373 latch SWmux: mux2g generic map(width => bus_width) port map (a => SW(1 to 4), b => SW(5 to 8), sel => BTN4, y => LD); end lab1_arch;

22. Sel y “00” a “01” b “10” c “11” d An n-line 4 x 1 multiplexer a(n-1:0) 8-line b(n-1 :0) 4 x 1 y(n-1 :0) c(n-1 :0) MUX d(n-1 :0) sel(1:0)

23. An 8-line 4 x 1 multiplexer library IEEE; use IEEE.std_logic_1164.all; entity mux4g is generic(width:positive); port ( a: in STD_LOGIC_VECTOR (width-1 downto 0); b: in STD_LOGIC_VECTOR (width-1 downto 0); c: in STD_LOGIC_VECTOR (width-1 downto 0); d: in STD_LOGIC_VECTOR (width-1 downto 0); sel: in STD_LOGIC_VECTOR (1 downto 0); y: out STD_LOGIC_VECTOR (width-1 downto 0) ); end mux4g;

24. Sel y “00” a “01” b “10” c “11” d Example of case statement architecture mux4g_arch of mux4g is begin process (sel, a, b, c, d) begin case sel is when "00" => y <= a; when "01" => y <= b; when "10" => y <= c; when others => y <= d; end case; end process; end mux4g_arch; Note implies operator => Must include ALL posibilities in case statement

25. VHDL Architecture Structure architecture name_arch of name is begin end name_arch; Signal assignments Processes contain sequential statements, but execute concurrently within the architecture body Concurrent statements Process 1 Concurrent statements Process 2 Concurrent statements

26. Optional process label VHDL Process P1: process (<sensitivity list) <variable declarations> begin <sequential statements> end process P1; Within a process: Variables are assigned using := and are updated immediately. Signals are assigned using <= and are updated at the end of the process.

27. Multiplexers • Multiplexers (Selectors) • Lab 1 – Behavioral VHDL -- Multiplexers • MUX as a Universal Element

28. Multiplexer as universal combinational module • connect input variables x to select inputs of multiplexer s • set data inputs to multiplexer equal to values of function for corresponding assignment of select variables • using a variable at data inputs reduces size of the multiplexer

29. Implementing a Boolean Function with a Multiplexer

30. Implementing a Four- Input Function with a Multiplexer

31. Networks with 2-input multiplexers

32. Implementation of SFs with network of MUXes

33. Design of networks with MUXes

34. Example

35. Ordering of variables in subtrees affects the number of MUXes

36. Example of Shannon’s Decomposition F = x3(x1 + x2x0) Implemented using a multiplexer network

37. F = x3(x1 + x2x0) Start with any variable - x0 for example x0 = 0 F = x3x1 x0 = 1 F = x3(x1 + x2)

38. F = x3(x1 + x2x0) Then x! for example x1 = 0 F = 0 x0 = 0 F = x3x1 x1 = 1 F = x3 x1 = 0 x0 = 1 F = x3x2 F = x3(x1 + x2) x1 = 1 F = x3

39. F = x3(x1 + x2x0) Then x2 for example x1 = 0 F = 0 x0 = 0 F = x3x1 x1 = 1 F = x3 x2 = 0 F = 0 x1 = 0 x0 = 1 F = x3x2 F = x3(x1 + x2) x2 = 1 F = x3 x1 = 1 F = x3

40. F = x3(x1 + x2x0) Inputs x1 = 0 F = 0 x0 = 0 F = x3x1 x1 = 1 F = x3 x2 = 0 F = 0 x1 = 0 x0 = 1 F = x3x2 F = x3(x1 + x2) x2 = 1 F = x3 x1 = 1 F = x3

41. F = x3(x1 + x2x0) MUX Select Lines x1 = 0 F = 0 x0 = 0 F = x3x1 x1 = 1 F = x3 x2 = 0 F = 0 x1 = 0 x0 = 1 F = x3x2 F = x3(x1 + x2) x2 = 1 F = x3 x1 = 1 F = x3

42. x1 = 0 F = 0 x0 = 0 F = x3x1 x1 = 1 F = x3 x2 = 0 F = 0 x1 = 0 x0 = 1 F = x3x2 F = x3(x1 + x2) x2 = 1 F = x3 x1 = 1 F = x3 x3x1 0 F 1 sel x3(x1 + x2) x0

43. x1 = 0 F = 0 x0 = 0 F = x3x1 x1 = 1 F = x3 x2 = 0 F = 0 x1 = 0 x0 = 1 F = x3x2 F = x3(x1 + x2) x2 = 1 F = x3 x1 = 1 F = x3 0 1 sel x3x1 0 x3 0 x1 F The branch for x0 = 0 1 sel x3(x1 + x2) x0

44. x1 = 0 F = 0 x0 = 0 F = x3x1 x1 = 1 F = x3 x2 = 0 F = 0 x1 = 0 x0 = 1 F = x3x2 F = x3(x1 + x2) x2 = 1 F = x3 x1 = 1 F = x3 0 0 1 1 sel sel x3x1 0 The branch for x0 = 1 x3 0 x1 F 1 sel x3x2 x0 x3 x1 x3(x1 + x2)

45. x1 = 0 F = 0 x0 = 0 F = x3x1 x1 = 1 F = x3 x2 = 0 F = 0 x1 = 0 x0 = 1 F = x3x2 F = x3(x1 + x2) x2 = 1 F = x3 x1 = 1 F = x3 0 0 0 1 1 1 sel sel sel x3x1 0 The branch for x1 = 0 x3 0 x1 F 0 1 sel x3 x0 x3 x2 x1 x3(x1 + x2) x3x2

46. 0 0 0 1 1 1 sel sel sel F = x3(x1 + x2x0) • Starting with x0 • Shannon’s Decomposition • 4 Multiplexers 0 x3 0 x1 F 0 1 sel x3 x0 x3 x2 x1

47. 0 0 1 1 sel sel F = x3(x1 + x2x0) • Starting with x1 • Shannon’s Decomposition • 3 Multiplexers 0 0 0 x0 F x3 x2 1 sel x3 x1

48. 16-input tree multiplexer