Modeling Dynamically Reconfigurable Systems via Rewriting-Logic (modeling and simulation of the FFT in Optimal Space)

1. Modeling Dynamically Reconfigurable Systems via Rewriting-Logic (modeling and simulation of the FFT in Optimal Space) C. Llanos2,4 ,M. Ayala-Rincón1,4, R. B. Nogueira2,4, R. P. Jacobi3,4 and R. W. Hartenstein5,61 Departamentos de Matemática, 2 EngenhariaMecânica e 3 Ciência da Computação 4 Universidade de Brasília 5 Fachbereich Informatik, 6 Kaiserslautern University of Technology2ndDagsthul Seminar onDynamically Reconfigurable ArchitecturesDagsthul, Germany, July 20-25, 2003 Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

2. Overview(Arvind aproach) • Applying rewriting techniques in hardware design [Arvind et al] • specification of correct processors • Cache protocols over memory systems • Specification of digital circuits • Specification and verification of network protocols Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

3. Characteristic of Arvind’s approach • rewriting is neither applied for simulation nor for verification • Proposal  Translate to Verilog! Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

4. Overview (using Haskell) • Bejesse et al use Haskell (a functional language) for circuit design, specification and verification • These ideas are implemented in LAVA system • This approach shows how the high level abstraction of functional languages is suitable for hardware design Lava approach takes advantage of high level abstraction provided by functional languages Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

5. Overview (Kapur Approach) • Kapur has used his well-known Rewriting Rule Laboratory - RRL for verifying arithmetic circuits • RRL is used to verify automatically properties of arithmetic hardware circuits (adders, multipliers, SRT division circuits) Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

6. Why Rewriting? • Rewriting is the formal framework of all functional languages • This fact allows us to work in more abstract levels • Rewriting assistant environments help in the task of formal verification of hardware Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

7. Rewriting Rules right side left side Premise to be hold lr if C Rewriting Rule Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

8. Premise to be hold Rewriting • Rewriting rules: lr ifC • Operational semantics: a rule is applied to a term, when its left-sidematches a sub-term, replacing the matched sub-term with the corresponding right-side of the rule. All that, whenever the premise C of the rule holds. Semantic: “lis replaced by r ifC is true” Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

9. Specifying Processors(Arvind’s proposal) SYS(mem,Proc) Data Mem +1 PC Int Mem Register File ALU PROC(ia,rf,prog) Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

10. Specifying Processors • Basic Processor • Single cycle, non pipelined, in-order execution • SYS := Sys(MEM,PROC) • PROC := Proc(ia, rf, prog) • AX Architecture • Instruction set: • r:=Loadc(v) r:=Loadpc • r:=Op(r1,r2) Jz(r1,r2) • r:=Load(r1) Store(r1,r2) Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

11. Defining Instruction of the processor by rewriting rules Conditional jump Jz-jump-rule: [Jz(r1, r2)] Proc(ia, rf, prog)  Proc(rf[r2], rf, prog) if im[ia] = jz(r1, r2) and rf[r1] = 0 Rewriting rules can implement state transitions in the processor Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

12. Gcd(6,15)  Result! Example: Euclid’s Algorithm for greatest common divisor (GCD) GCD Mod Rule Gcd(a, b)  Gcd(a-b, b) if (a  b)  (b  0) GCD Flip Rule Gcd(a, b)  Gcd (b, a) if a < b • The term Gcd(6,15) can be reduced by applying the Mod and Flip rules Flip Gcd(15,6)  Mod Gcd (9, 6)  Mod Gcd(3, 6)  Flip Gcd (6, 3)  ModGcd(3,3)  Mod Gcd(3,0) Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

13. Characteristic of Rewriting • Rules are applied non-deterministically • Controlling the execution of rules can be accomplished by logic Rewriting-Logic = Rewriting Rules + Strategies Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

14. Examples of Rewriting Oriented Environments • ELAN: • Maude: it has great flexibility for defining types and ease manipulation of strategies • It’s necessary to do more effort for description • it provides model checking useful for hardware verification Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

15. R2 Op2 R1 C1 Ar1 Ar2 Op1 P1 P2 Example of a Reconfigurable Architecture functional Units Constant Register Address register Address register Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

16. Example of Reconfigurable Architecture R2 At some time the configuration can be specified * Op2 R1 C1 011 100 Ar1 Ar2 AND 1 100 Op1 P1 P2 Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

17. R2 * Op2 R1 C1 011 100 Ar1 Ar2 AND 1 100 Op1 P1 P2 Describing Architectures in ELAN Problem: how can this architecture be described in ELAN Using and defining types It’s possible to describe fixed parts and reconfigurable ones const(@) : ( complexUnit ) Const; port(@) : ( complexUnit ) Port; reg(@) : ( complexUnit ) Reg; addr(@) : ( int ) Addr; @,@,@,@,@ : ( int Port Port Reg Reg ) fixMAC; @,@,@,@,@ : ( Addr Addr Const OpUnit OpUnit ) recMAC; [ @ # @ ] : ( fixMAC recMAC ) MAC; Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

18. Describing more Complex Architectures R2 R2 R2 Op2 Op2 Op2    R1 R1 R1 C1 C1 C1 Ar1 Ar1 Ar1 Ar2 Ar2 Ar2 Op1 Op1 Op1 P1 P1 P1 P2 P2 P2 Processor @,@,@,@,@ : ( int Port Port Reg Reg ) fixMAC; @,@,@,@,@ : ( Addr Addr Const OpUnit OpUnit ) recMAC; [ @ # @ ] : ( fixMAC recMAC ) MAC; < @ @ @ @ @ @ @ @ @ @ > : ( int rArrayStruct MAC MAC MAC MAC MAC MAC MAC MAC )Proc; Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

19. How the Execution Process is described in the ELAN system < [0,port(cPort1),port(cPort2),reg(cReg1),reg(cReg2)# addr1,addr2,const(cConst1),op1,op2] > < [0,port(cPort1),port(cPort2),reg(cRegRes1),reg(cRegRes2) # addr1,addr2,const(cConst1),op1,op2] > where cRegRes1 :=() operate(cPort1,cPort2,op1) where cRegRes2 :=() operate(cReg1,cConst1,op2) Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

20. How the Reconfiguration Process is described in ELAN system [] reconfigure(MACsArray( [ fix0 # rec0 ] ) MACsArray([ fix0 # getRecMAC(MAConfig0) ] ) Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

21. Using Strategies in ELAN strategies for Proc implicit [] process input; repeat*(reconfiguration;propagation;execution); output end end • Using strategies for guiding the application of the rules • Strategies in ELAN allow to separate execution and reconfiguration steps • This approach allows a closer specification to transference register description (RTL Description) Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

22. a0 b0 a4 b1 a2 b2 a6 b3 a1 b4 a5 b5 a3 b6 a7 b7 Reconfiguration for FFT Number of reconfiguration = ln(n) + 1 Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

23. 2 4 5 6 7 0 1 3 FFT in Optimal Space MAC0 MAC1 MAC2 MAC3 MAC4 MAC5 MAC6 MAC7 Interconnections in reconfiguration step 3 Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

24. An Execution Rule for a pair of MACs [MAC01] < [0,port(cPort1),port(cPort2),reg(cReg1),reg(cReg2)# addr1,addr2,const(cConst1),op1,op2] [1,port(cPort3),port(cPort4),reg(cReg3),reg(cReg4)# addr3,addr4,const(cConst2),op3,op4] > < [0,port(cPort1),port(cPort2),reg(cRegRes1),reg(cRegRes2) # addr1,addr2,const(cConst1),op1,op2] [1,port(cPort3),port(cPort4),reg(cRegRes3),reg(cRegRes4) # addr3,addr4,const(cConst2),op3,op4] > where cRegRes1:= () operate( cPort1,cPort2,op1 ) where cRegRes2:= () operate( cRegRes1,cConst1,op2 ) where cRegRes3 := () operate( cPort3,cPort4,op3 ) where cRegRes4 := () operate( cRegRes3,cConst2,op4 ) Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

25. A Reconfiguration Rule for a pair of MACs [reconfiguration] < [ fix0 # rec0 ] [ fix1 # rec1 ] > < [ fix0 # addr(0),addr(2),const( < 1,0000 0,0000 > ), < + >,< * > ] [ fix1 # addr(1),addr(3),const( < 1,0000 0,0000 > ), < + >,< * > ] > Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

26. Reconfigurable Interconnection Network Reconfigurable Interconnection Network A Pipelined Reconfigurable FFT (eliminating the reconfiguration overhead) • While one Mac array is being reconfigured the other array is computing one step of FFT Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

27. Advantages of ELAN Environment • ELAN has the advantage of an embedded inference engine • a flexible type definition mechanism (data and operators) • a powerful manipulation of typed expressions through rules and meta-rules • the availability of logical strategies to control their application. Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems

28. Conclusions • The high abstraction of Rewriting Environments makes design exploration easier • Using ELAN is possible to simulate the description of the architecture • Descriptions in ELAN are close to the physical architecture Modeling DRS via Rewriting-Logic, 2nd Dagstuhl Seminar on Dynamically Reconfigurable Systems