ECE 697F Reconfigurable Computing Lecture 6 Mapping to Embedded Memory and PLAs

1. ECE 697FReconfigurable ComputingLecture 6Mapping to Embedded Memory and PLAs

2. Outline • Overview • Targeted to existing hybrid PLA/LUT FPGAs • Area and timing-constrained mapping • HybridMap • Graph-based approach • Post-map product term estimation • Results • Comparisons with existing approaches • Mapping to Apex20KE • Acknowledgement: Srini Krishnamoorthy

3. Output Reset Inputs Hybrid FPGAs with LUTs and PLAs • LUTs • Dense logic, small number of inputs • Special circuitry for arithmetic logic • PLAs • For wide fanin, low logic density structures • Control-logic (e.g. Finite State Machines) • Device containing both resources • Move maximum logic to PLAs • Implement remaining logic in LUTs

4. Hybrid FPGAs • Resources • LUT blocks and Pterm macrocells • Objective • Minimize 4-LUT area subject to design performance constraints • Potential use: smaller devices • Key factor • Efficient partitioning of design components

5. Global Interconnect LE 1 LE 1 PLA LE 2 LE 2 LE 3 LE 3 LE 4 LE 4 LE 5 LE 5 LE 6 LE 6 LE 7 LE 7 LE 8 LE 8 Local Interconnects LUTs Hybrid FPGA (Similar to APEX20KE Megalab)

6. Pterm Estimation Subgraph Merging Area Estimation HybridMap Flow Design Entry SIS Tech. Independent Optimization Vendor-Specific CAD Node Partitioning PLA Mapping Pterm Estimation PLA Subgraphs LUT Mapping LUT Identification Subgraph Generation LUT Partition Place and Route Area Estimation Mapped Design

7. LUT Identification I1 I2 I3 I4 I5 I6 I7 • Design initially reduced to 2-input gates • Topological traversal starting from primary inputs • Input count to any LUT cluster is less than K • A node always belongs to the cluster that minimizes delay • LUT clusters are preliminary • Used to estimate LUT count • Similar to DAG-map (Lawler’s alg) LUT Cluster O1 O2 O3

8. Subgraph Generation O2 O1 O Maximum Fanout Free Subgraph (MFFS) Maximum Fanout Free Cone (MFFC) - All edges except output edge(s) stay within the cone

9. Subgraph Generation • Extract a multi-input, multi-output subgraph • Root set determination • Identify subgraph outputs • Forward traversal • Subgraph identification • Identify the subgraph inputs • Backward traversal V Search Root-set determination (Forward BFS) Condition: Nodes at each level <= Opla

10. Subgraph Identification I0 I1 I2 V Search I3 O1 O2 O3 O4 O5 Subgraph determination (Backward BFS) Condition: Inputs <= Ipla, Backward breadth first search until input constraint met

11. I1 I2 I3 I4 V basic hill climbing basic Search O1 O2 Reconvergent Paths • Hill-climbing approach • Start basic subgraph search algorithm from v • If nodes encountered > Opla • Neglect PLA output constraint • Continue search • When nodes encountered < Opla • Revert back to basic search algorithm

12. Subgraph Pruning • Hill-climbing subgraph may violate PLA I/O constraints • Need to prune • Pruning steps • Collapse subgraph to two-level form • Remove outputs requiring least inputs • Outputs requiring K inputs (single LUT removal) • Minimal multi-LUT removal PLA

13. SG 1 SG 2 Subgraph Combining • Smaller subgraphs can be packed onto a single PLA • Combine based on cost function • LUT savings due to merging • Input sharing • Pterm count • Choose 2 subgraphs for merging based on combined feasibility in terms of PLA inputs, outputs and Pterms • Invoke Pterm estimator

14. 4-input nodes 2-input nodes Total LUT Savings R=1 R=5 R=10 R=5 R=5 R=10 316 1255 2358 364 1367 2357 R Number of PLAs Results: Effect of Initial Graph Node Size • Resources: 4-LUTs, 32 Input 16 Output 32 Pterm Macrocells • 2-Input case • Identify PLA Partitions • Map rest to LUTs using Flowmap • 4-Input case • Map initially to LUTs • Extract PLA Partitions • 13 MCNC benchmarks (8939 LUTs initially)

15. Mapping to APEX20KE-1 Altera software: Quartus v2000.02 Timing Constrained Case : 8% LUT Reduction Unconstrained Case : 14% LUT Reduction

16. Summary • Hybrid FPGAs: A challenging problem • Subgraph based approach to technology mapping • Pterm based macrocells, Pterm estimation • Unconstrained and timing constrained mapping • Delay and area estimation an important part of the mapping process • Results • Pterm estimation improves LUT coverage by about 12% • Apex20KE devices • Unconstrained : 14% 4-LUT savings • Timing constrained : 8% 4-LUT savings

17. Notes for Transcription Assignment • Focus on one main point • Write an outline • Check English and spelling

18. Transcription • Introduction • Lecture summary • Summary of papers • Contrast of papers • Conclusion • References

19. Overview • Paper should be focused on a primary goal • May not be obvious until after reading • What will the reader take away from this work • Is there a common theme • Introduction • Should summarize the entire paper. • Each paragraph presents a main idea • Ideas should be detailed but sufficiently high-level. • Results paragraph should present a result to support the theme.

20. Tackling the Body • Lecture summary • Brief review of the lecture • Focus on main point • Should flow seamlessly into/with papers • I can make powerpoint available • Summary of papers • Discussion of main approaches • Important new techniques • Main point made by author • Main result/results

21. Contrasting the Papers • Pick categories for comparison • Should be three to four • Each section should contrast a different category. • Try to focus on specific details of each paper • Consider using a table to supplement text. • Helps clarify detailed comparison • Focus on comparison rather than restating the details

22. Other Tips • Have a friend review your work. • Try to keep sentences focused • Subject – verb – description • Avoid using first person. • Write a detailed outline before you write any text. • Give yourself plenty of time • You should have at least four or five references.