GROUP 5 Mohmmad Alam Wayne Buckhanan Hubert George

1. University of Notre Dame Department of Electrical EngineeringEE60546 GROUP 5 Mohmmad Alam Wayne Buckhanan Hubert George

2. Diode fabrication and testing Challenges Modification of IC Fab layout Via etching Results Nmos process design and fabrication Limitations and design (Enh. & Dep. Mode) Gate height dilemma Outline

3. LOCOS N-Well mask vs P-select Phosphorus diffusion Opted not to do drive in Interlevel dielectric Etch vias Sputter - back/Ti/AlSi Al etch Testing TLM data Diodes

4. Using mask number 0 (Align etch mark), number V (P-Select area definition), mask VI – (Contact holes) and mask VII – (Metal pattern). Using masks number I (N-Well area definition), mask VI – (Contact holes) and mask VII – (Metal pattern).

6. Typical TLM Data

7. Diode

8. Other Structures

9. Comparing Structures

10. Best TLM Data

12. LOCOS Boron diffusion every time at temp Gate oxides 42 min 1100 dry ~1000Ang Photolithography, etch for depletion mode active regions 1 min 1100 dry ~100Ang Polysilicon *Etch poly *Phosphorus diffusion *Drive in *Interlevel dielectric *Vias *Metal Nmos

17. Two different gate oxide thicknesses to reach the two threshold voltages for the two types of transistors (Enhancement and Depletion). • (Dt)_total = sum of D_i*t_i • D for 1200degC ~10^-10, 1100 ~10^-11, 925 ~10^-13 • 60min dry 20min wet @1200 -> ~5000Angstrom Field Oxide

19. Light/dark opted to only use positive PR two dark field - contacts and depletion 'P' vs 'I' Fiducials 5" chrome plate ~= 126.66mm != 125mm Standard keys 5x5 job Spacing Shutters Alignment test Masks

20. Doht!

21. After 30um corrections

22. Any Questions… ?