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ECT 357

ECT 357. Ch 18 UART. Today’s Quote: Be careful that your marriage doesn’t become a duel instead of a duet. Let us therefore follow after the things which make for peace, and things wherewith one may edify another. Romans 14:19. USART.

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ECT 357

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  1. ECT 357 Ch 18 UART

  2. Today’s Quote: Be careful that your marriage doesn’t become a duel instead of a duet. Let us therefore follow after the things which make for peace, and things wherewith one may edify another. Romans 14:19

  3. USART The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.)

  4. USART Modes The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous - Master (half-duplex) • Synchronous - Slave (half-duplex)

  5. USART Pin Setup In order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter: • bit SPEN (RCSTA<7>) must be set (= 1), • bit TRISC<6> must be cleared (= 0), and • bit TRISC<7> must be set (=1).

  6. USART Baud Rate Generator The baud rate generator supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored.

  7. SPBRG Example Setting

  8. USART Asynchronous Mode In this mode, the USART uses standard non-return-to zero (NRZ) format (one START bit, eight or nine data bits and one STOP bit). The most common data format is 8-bits. The USART transmits and receives the LSB first. The USART’s transmitter and receiver are functionally independent, but use the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP.

  9. USART Transmit Block Diagram

  10. Asynchronous Transmit Setup 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit TXIE. 4. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. 5. Enable the transmission by setting bit TXEN, which will also set bit TXIF. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Load data to the TXREG register (starts transmission).

  11. USART Receive Block Diagram

  12. Asynchronous Receive Setup 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired,set bit BRGH. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit RCIE. 4. If 9-bit reception is desired, set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enablebit RCIE was set. 7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurredduring reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) areset.

  13. 9 bit mode with Address Detect This mode would typically be used in RS-485 systems. 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is required,set the BRGH bit. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be acknowledged if theRCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as readbit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into thereceive buffer and interrupt the CPU.

  14. USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA<7>).

  15. Synchronous Transmission

  16. Synchronous Reception Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence.

  17. Synchronous Reception

  18. USART Synchronous Slave Mode Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>).

  19. The operation of the Synchronous Master and Slavemodes is identical, except in the case of the SLEEPmode and bit SREN, which is a “don't care” in Slavemode.If receive is enabled by setting bit CREN prior to theSLEEP instruction, then a word may be received duringSLEEP. On completely receiving the word, the RSRregister will transfer the data to the RCREG register,and if enable bit RCIE bit is set, the interrupt generatedwill wake the chip from SLEEP. If the global interrupt isenabled, the program will branch to the interrupt vector.setting bits SYNC and SPEN and clearing bitCSRC.

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