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ECT 358

ECT 358. Lecture 3b FPGA’s. If you don’t stand for something you’ll fall for anything. If you do not stand firm in your faith, you will not stand at all. Isaiah 7:9b. Field-Programmable Gate Array (FPGA). Channel Based interconnection fabric Lookup Tables Configuration Memory

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ECT 358

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  1. ECT 358 Lecture 3b FPGA’s

  2. If you don’t stand for something you’ll fall for anything. If you do not stand firm in your faith, you will not stand at all. Isaiah 7:9b

  3. Field-Programmable Gate Array (FPGA) • Channel Based interconnection fabric • Lookup Tables • Configuration Memory • Array of Programmable Function Units • Features • Architecture • # of gates • Program volatility • Speed • Programmability • SRAM based • Block memory • Distributed memory • Global signals

  4. FPGA Architecture • Array of Programmable Function Units • Implement combinational and sequential logic • Fixed Programmable Interconnection Fabric • Establishes routing of signals • Configuration Memory • SRAM based • Programs functionality of device • I/O Resources • Interface between device and environment

  5. FPGA Architecture

  6. FPGA Types • Antifuse • High voltage breaks down dielectric • One time write • Retains memory • EEPROM • Charged floating gate • Programmed by high voltage • Programmed offline • SRAM • Loses programming with power

  7. FPGA Programming • Must be reprogrammed after blackout • Boundless variety of applications • Reconfigured via a processor • Execute test system on host system • Easily reprogrammed remotely

  8. Altera Flex 8000 FPGA architecture • Logic Element matrix • FastTrack Interconnect • Ends connected to I/O • Logic Array Blocks (LAB) • 8 Logic Elements (LE) / LAB • 4 inputs • 4 signals (clocks, clear preset control) • Programmable register • Carry and cascade chains

  9. Altera Flex 8000 FPGA architecture

  10. Altera Flex 8000 Uses • Digital Signal Processing • Wide Data Path Integration • Data Transformations • Bus Interfaces • Coprocessor Functions • TTL integration • High Speed Controllers

  11. Altera Flex Logic Element • 4 inputs • 4 terms for AND or OR • Look up table • 4 signals (clocks, clear preset control) • Programmable register • Carry and cascade chains • AND or OR up to 8 • Carry/Preset Logic

  12. Altera Flex Logic Element

  13. ALtera Flex Embedded RAM/ROM • Programmed as RAM or ROM • 1 For each row (24 lines) • 2K memory • Row Interconnect serves as address bus • Row or Column Interconnect serves as data bus • 1 logic level complex functions • Combines flexibility of CPLD with density and efficiency of an embedded gate array

  14. ALtera Flex Embedded RAM/ROM

  15. Xilinx Spartan Architecture • Array of configurable logic blocks • Local and global routing resources • I/O blocks • Programmable I/O buffers • SRAM based configuration memory

  16. Xilinx Spartan Architecture

  17. Xilinx Configurable Logic Block • Look up table (LUT) • Multiplexers • Registers • Control Signals • 3 function generators (can be used as RAM) • 2 storage devices • Outputs connected to Interconnect network

  18. Xilinx Configurable Logic Block

  19. Xilinx Interconnect Resources • General Purpose switching and routing • Single Width Lines • Double Width Lines • Long Lines • Switch Boxes

  20. Xilinx Interconnect Resources

  21. Switch Matrix Transmission Gates • Programmable Interconnection Points (PIP) • State determined by SRAM cell • Path can be reconfigured • Connects vertical lines to horizontal lines

  22. Switch Matrix Transmission Gates

  23. Xilinx I/O Block • Programmable • Buffers with TTL/CMOS levels • Input/Output/Bidirectional • Skew and Slew control • Global set and reset • Separate clocks • Pull Up/Down

  24. Xilinx I/O Block

  25. Single Port RAM Uses • FIFO • Shift Register • Scratch pad memory Uses look up tables Can be cascaded Synchronous write and asynchronous read

  26. Single Port RAM

  27. Dual Port RAM • Emulated in Spartan • 2 single port RAM’s • Common write port • 2 asynchronous read ports

  28. Dual Port RAM

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