IP Based Design

1. IP Based Design Jin-seong Jeong and Ram Kumar EE202A Fall 2001 Student Presentation

2. Introduction • IP – Intellectual Property • Pre-designed • Pre-verified • Re-usable • H/W S/W Functional Blocks • Examples • Processor – Leon Sparc, IBM PPC • Multimedia – MPEG Decoder, JPEG Compression • Controllers – USB, PCI • Networking - Ethernet

3. Core Types • Soft Cores • HDL Description • Flexible – Can be changed to suit an application • Technology Independent – Can be re-synthesized across processes • Firm Cores • Gate-level netlists to be placed and routed • Hard Cores • Ready to use • Include layout and timing (Tech. Dependant) • Mostly processors and memory

4. Design Issues • IP Specification • IP Implementation • Reusability • Customizable/Portable • Validation • Communication/Interface Synthesis • Socketing Standards • Communication between software modules • Simulation and Verification • IP Protection

5. IP Repository IP Component IP Implementation IP Component IP Implementation IP Component IP Specification Behavior Code RTL Code PORT MAP JAVA CLASS Clock VERILOG Input Port TEXT DATA IP Specification Output Port Area InOut Port Clock TIMING Power PORT LIST Port A Setup Hold Port A Throughput Port B Setup Hold Timing Constraints Port B Port Map IP Specification – JAVACAD DOM

6. MODAL PROCESS IPCHINOOK - Modal Processes • Concurrent Interacting modules: Ports, Handlers and modes • Ports: Logical communication contact points for inter-process comm. • Mode: State of a process, maps inputs to handlers • Handlers: Code with run to completion semantics • Dispatch message to output ports • Vote for activation-deactivation of modes HANDLERS MODAL PROCESS IO PORT MODAL PROCESS MESSAGES

7. WATCH seqLoop SHOWN WS WATCH-UI SS STOP WATCH AS SHOWN STOPWATCH-UI ACT ALARM SHOWN Modal Process Mode ALARM-UI Control Composition - Wrist Watch • Abstract Control Types (ACTs) • Control co-ordination between components • Establish automatically maintained relationships between modes.

8. Mode Manager Synthesis • Coordinating between processes • Part of run-time system managing control communication according to ACTs • Handles state maintenance task • Centralized or distributed mode manager • Depends on target architecture • Uni-processor or Multi-processor • Centralized mode manager • Executed on a uni-processor • Processes run mode-synchronously • Processes blocked, No handlers run till mode changes are resolved

9. Core Implementation • Synopsys DesignWare Flow • RTL Coding • In adherence to the Re-use Methodology Manual • Unit-level verification • Small “throw away” test bench for exhaustive unit test prior to integration with top-level IP-block • Code coverage analysis • Line Coverage • Toggle Coverage • Condition Coverage • Integration and Verification of core

10. Models • A representation of a IP-block used in a particular step of the design or verification flow • Bus Functional Model • Simulation model used to verify interfaces around core • Full Functional Model • Simulation model representing the full functionality of the core • Instruction Set Architecture Model • Architecture level model for testing the architecture specific software for a processor core

11. Communication Synthesis • Abstract communication protocols on target • Abstract Specification • Output Port: Blocking style, deadline constraint • Input Port: Queue size, overflow behavior • Multi-hop deadline distribution • Hop-processes: Route messages • Distribute deadline along message path • Partitioning takes global view by accounting all bus traffic in system • Bus protocol attribute synthesis • Message Ids, Processor Ids, priorities • Device driver synthesis

12. Producer Process Consumer Process OutPort Inport Message Router Device Driver Device Driver Comm. Chip Comm. Chip Communication Synthesis

13. Interface Synthesis • Problem • Given two communicating design actors exchanging data, and a description of the two protocols that each one of them uses to transfer the data, determine an interface so that data transfers are consistent with both protocols.

14. Protocol specification • Protocol : legal sequences of values that may appear on the ports from the onset to the end of the data transfer • Symbol : a tuple composed of the values on the ports • Protocol is simply a set of strings of symbols • The Goal • To obtain a FSM that when placed between the two modules implementing the specified protocols would make the communication possible

15. Protocol specification example Type byte bit[7:0] Type yow { byte a; byte b} Protocol serial of type yow { Master bit start, byte bus; Term null() { 0, - } Term one(byte b) { 1, b } Term two(byte b) { 0, b} Serial(yow y) { null()*, one(y.a), two(y.b) } } Protocol handshk of type yow { master bit trigger, byte bus; term wait(bit t){ t, - } term get(bit t, byte b) { t, b } handshk(yow y) { wait(0)*,get(1,y.a)+,get(0,y.b)+ } }

16. Synthesis Algorithm

17. Simulations and Verifications • Simulations • Able to simulate at each design abstract levels • Co-simulation • Verification • Functionality tests to verify the basic operation of the IP and compliance to any standards • Deep corner cases to verify the correct functionality of the IP under unusual conditions • Random testing • Silicon prototyping

18. Conclusion • IP component selection and matching • Standards to promote IP reuse • VSIA – Virtual Socket Interface Alliance • Retargetability through communication and interface synthesis • Comprehensive hardware/software co-synthesis framework • Efficient simulation techniques let designers validate their design at different stages of synthesis

19. References • Zhang, T.; Benini, L.; De Micheli, G. Component selection and matching for IP-based design Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001. Proceedings , 2001 Page(s): 40 –46 • Kucukcakar, K.Analysis of emerging core-based design lifecycle Computer-Aided Design, 1998. ICCAD 98. Digest of Technical Papers. 1998 IEEE/ACM International Conference on , 1998 Page(s): 445 –449 • Pai Chou; Ortega, R.; Hines, K.; Partridge, K.; Borriello, G.IPCHINOOK: an integrated IP-based design framework for distributed embedded systems Design Automation Conference, 1999. Proceedings. 36th , 1999 Page(s): 44 –49 • Passerone, R.; Rowson, J.A.; Sangiovanni-Vincentelli, A.Automatic synthesis of interfaces between incompatible protocolsDesign Automation Conference, 1998. Proceedings , 1998 Page(s): 8 –13 • Savage, W.; Chilton, J.; Camposano, R.IP reuse in the system on a chip era System Synthesis, 2000. Proceedings. The 13th International Symposium on , 2000 Page(s): 2 –7 • http://www1.ics.uci.edu/~rgupta/cores.html • IPCHINOOK http://www.cs.washington.edu/research/chinook/ • Design & reuse http://www.us.design-reuse.com • Virtual Socket Interface Alliance http://www.vsia.org • Open Cores http://www.opencores.org