EE121 John Wakerly Lecture #14

1. EE121 John Wakerly Lecture #14 Read-only memories (review) Static read/write memories Dynamic read/write memories

2. Read-Only Memories • Program storage • Boot ROM for personal computers • Complete application storage for embedded systems.

3. Two-dimensional decoding

4. Larger example, 32Kx8 ROM

5. Typical commercial EEPROMs

6. Microprocessor EPROM application

7. ROM control and I/O signals

8. ROM timing

9. Read/Write Memories • a.k.a. “RAM” (Random Access Memory) • Volatility • Most RAMs lose their memory when power is removed • NVRAM = RAM + battery • Or use EEPROM • SRAM (Static RAM) • Memory behaves like latches or flip-flops • DRAM (Dynamic Memory) • Memory lasts only for a few milliseconds • Must “refresh” locations by reading or writing

10. SRAM

11. SRAM operation • Individual bits are D latches, notedge-triggered D flip-flops. • Fewer transistors per cell. • Implications for write operations: • Address must be stable before writing cell. • Data must be stable before ending a write.

12. SRAM array

13. SRAM control lines • Chip select • Output enable • Write enable

14. SRAM read timing • Similar to ROM read timing

15. SRAM write timing • Address must be stable before and after write-enable is asserted. • Data is latched on trailing edge of (WE & CS).

16. Bidirectional data in and out pins • Use the same data pins for reads and writes • Especially common on wide devices • Makes sense when used with microprocessor buses (also bidirectional)

17. SRAM devices • Similar to ROM packages 28-pin DIPs 32-pin DIPs

18. Synchronous SRAMs • Use latch-type SRAM cells internally • Put registers in front of address and control (and maybe data) for easier interfacing with synchronous systems at high speeds • E.g., Pentium cache RAMs

19. DRAM (Dynamic RAMs) • SRAMs typically use six transistors per bit of storage. • DRAMs use only onetransistor per bit: • 1/0 = capacitorcharged/discharged

20. DRAM read operations • Precharge bit line to VDD/2. • Take the word line HIGH. • Detect whether current flows into or out of the cell. • Note: cell contents are destroyed by the read! • Must write the bit value back after reading.

21. DRAM write operations • Take the word line HIGH. • Set the bit line LOW or HIGH to store 0 or 1. • Take the word line LOW. • Note: The stored charge for a 1 will eventually leak off.

22. DRAM charge leakage • Typical devices require each cell to be refreshed once every 4 to 64 mS. • During “suspended” operation, notebook computers use power mainly for DRAM refresh.

23. DRAM-chip internal organization 64K x 1DRAM

24. RAS/CAS operation • Row Address Strobe, Column Address Strobe • n address bits are provided in two steps using n/2 pins, referenced to the falling edges of RAS_L and CAS_L • Traditional method of DRAM operation for 20 years. • Now being supplanted by synchronous, clocked interfaces in SDRAM (synchronous DRAM).

25. DRAM read timing

26. DRAM refresh timing

27. DRAM write timing

28. Next Time • CPLDs • FPGAs