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Proposal : Design of a 2.5 Gbps Radiation Tolerant SerDes for the CBM–DAQ in 180 nm CMOS process

Proposal : Design of a 2.5 Gbps Radiation Tolerant SerDes for the CBM–DAQ in 180 nm CMOS process. Pradeep Banerjee, Dr. T. K. Bhattacharyya, E & ECE Dept., Indian Institute of Technology, Kharagpur CBM Collaboration Meeting, VECC, Kolkata 31 st July, 2010. Outline.

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Proposal : Design of a 2.5 Gbps Radiation Tolerant SerDes for the CBM–DAQ in 180 nm CMOS process

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  1. Proposal: Design of a 2.5 Gbps Radiation Tolerant SerDes for the CBM–DAQ in 180 nm CMOS process Pradeep Banerjee, Dr. T. K. Bhattacharyya, E & ECE Dept., Indian Institute of Technology, Kharagpur CBM Collaboration Meeting, VECC, Kolkata 31st July, 2010

  2. Outline • New Proposal for a separate Data Aggregation chip • Architecture and Circuit Options for the High speed Serializer • Some aspects of Radiation Tolerant design in deep submicron CMOS • Budget Proposal • Activities at the RF IC group at AVLSI Lab, IIT KGP CBM Collaboration Meeting, VECC

  3. The CBM Generic Read-out Chain DAQchain Detector Sub-System FLES Front-EndBoard Detector Read-OutController Active BufferBoard Data CombinerBoard First LevelEvent Selector FEB ROC DCB ABB FLES Data &Control Data Control Data DCS Sync TNet FEE DAQInterface Local Pre-Processing DigitizationCustom ASIC DAQFLESInterface FPGA Coprocessor Buffering SystemSynchronization Event Selection CPU Farm Slide Info: Walter F.J. Müller, GSI CBM Collaboration Meeting, VECC 3

  4. STS Data Rates – Aggregation Very few chip in inner region have hit rate > 32 MHz > 90% of chips have hit rates in 2...16 MHz range AMPLE SCOPE FOR DATA AGGREGATION 31.25 MHz hit rate (80 bits/hit)  2.5 Gbps Au+Au @ 25 AGev107 evt/sec Hit rate per chip Statistics Slide Data from: Walter F.J. Müller, GSI CBM Collaboration Meeting, VECC 4

  5. STS FEB Type and Link Distribution • 38 chips exceed 2.0 Gbps: 29 with 2.0 … 2.4; 9 with 2.4 … 3.2; • # of FEBs and type distributions varies for stations • All 8 chips combined give less than 2.5 Gbps (Aggregation Possible) --> FEBa8 • A single chip gives data worth 2.5 Gbps (No Aggregation possible) --> FEBa1 Slide Data from: Walter F.J. Müller, GSI CBM Collaboration Meeting, VECC 5

  6. Data Aggregation on separate chip - Communication hub • Motivation: • Data Aggregation: In most cases 2,4, or 8 CBM-XYTER chips (FEBa2, FEBa4, FEBa8, resp.) can be aggregated to fill a 2.5 Gbps link • Increase the bandwidth available per link • Reduce the number of Optical Links • Schemes: • Embedded (aggregation integrated in CBM-XYTER) • Data aggregation and Traffic Managementwith a separate Communication Controller Asic • Clock Distribution • Slow control traffic • Data Readout traffic Communication ‘hub’ CBM Collaboration Meeting, VECC 6

  7. Xyter #1 A peep into some feasible ‘Hub’ ASIC Requirements – Initial Proposal from Dr. Muller • Capacity for data aggregation from several Readout-ASICs into a single output link • 1 ‘hub’ ASIC may contain 6 high speed Serializers : 6 Tx for data  15 Gbps serviceable data bandwidth • 1 Rx – 1 Tx channel for clock, sync, control • 250 MHz sys clock as Transmit clk  500 Mbps (DDR LVDS) input interface • 5-8 LVDS o/p links (each 500 Mbps) per chip (8 chips per FEB) • FEBa8 case : 1 LVDS link per chip: combinedata upto 6 FEBs (48 LVDS links) per Hub • FEBa1 case : All 6 LVDS links (single chip) per Serializer • Cross-Connect Topology: Dynamic load balancing b/w the 6 output links desirable FEB sys_clk HUB Asic LVDS I/O PM Hub-Core @250 MHz Sys_clk SerDes#1 Six 2.5 Gbps o/p links 5-8 LVDS links (500 Mbps) per chip SerDes#2 Xyter #2 Detector i/f #8 #6 clock, sync, control i/f CBM Collaboration Meeting, VECC ‘Hub’ Idea: Walter F.J. Müller, GSI 7

  8. 2.5 Gbps o/p links clock, sync, control i/f 2.5 Gbps o/p links clock, sync, control i/f HUB Asic sys_clk Serializer #1 HUB CORE 5-8 LVDS links (500 Mbps) per chip Serializer #2 PROTOCOL ENGINE PROTOCOL ENGINE LVDS Rx FEB Tx SERDES CMU sys_clk DeSerializer#1 5-8 LVDS links (500 Mbps) per chip DeSerializer#2 FEB Rx PROTOCOL ENGINE LVDS Tx PROTOCOL ENGINE SERDES CDR + Jitter Cleaner @250 MHz @2.5 GHz CBM Collaboration Meeting, VECC

  9. High Speed Serializer Core • Design of the following functional blocks: • High speed SerDes (2.5 Gbps) • Clock Multiplier Unit (CMU) • Clock and Data Recovery (CDR) • Output Driving Logic (impedance matched) • Technology: • CMOS process of interest: UMC 180 nm (Available through Europractice) • Beneficial Features for Radiation tolerant design: • Retrograde wells • Shallow Trench Isolation CBM Collaboration Meeting, VECC 8

  10. Serializer “Primer” • Parallel-load Shift register: • Cascade of flip-flops and 2-to-1 multiplexers • Operation speed is limited by: • Clock to Q delay • Mux delay • Flip-flop setup time • Maximum frequency: • 1/(tcq + tmux + tsetup) • Static Flip-Flops: • Operation @ 2.5 Gbps  T = 400 ps • Speed constraint • Can we use Dynamic Flip-Flops? • No, they are sensitive to SEUs • Other high speed options: • Current Mode Logic CBM Collaboration Meeting, VECC 9

  11. 2.5 Gbps Serializer ASIC block diagram BIST gen TXP D(0:9) 2.5 Gbps 50 ohm driver Word Mux 10 bit Serializer d(0:9) TXN 250 MHz Tx Clk 1.25 GHz load 2.5 GHz PLL Ref 2.5 GHz Clock Generator PLL Not shown: FIFOs, Arbitration logic (token ring), 8B/10B Encoders CBM Collaboration Meeting, VECC 10

  12. Multiple Serializer Core: Design Challenges • Jitter-free Clock signalMinimize noise contribution of VCO (Total serial o/p jitter < 120 ps for BER ~ 10-12) • Switching noise generated by digital logic in ASIC • Constantphase relationship b/w VCO and Sys clock (400 ps bit time) • MultipleSerializer cores per chip: • Power efficiency, ASIC footprint • Sharinga single frequency multiplier among several Serializer cores in the same ASIC : • Distributing multi-gigahertz clocks over an extended distance consumes lot of power • Signal integrity issues  percentage of area saved as a function of the number of cores for a PLL that is half the size of a Serializer core saturates beyond 4 • Careful planning on circuit layout  buffering high speed clock in cascade actually worsens jitter performance • De-Serializer: CDR complexity CBM Collaboration Meeting, VECC 11

  13. Serializer – Dual phase Architecture CBM Collaboration Meeting, VECC 12

  14. Serializer – Dual phase Architecture … • Word-clock = (1/10) * VCO Clock ( VCO Clock= 2.5 GHz) • Bit-clock = (1/2) * VCO Clock • Multiphase Clock generation for further reduction of clocking speed • Issues: Duty cycle distortion jitter CBM Collaboration Meeting, VECC 13

  15. CDR Specifications • Main Contribution to Serial Data Jitter: Bandwidth limited Channel Jitter (White Noise spectrum) • Jitter Tolerance vs Jitter Transfer Trade-off • The jitter tolerance of CDR has the same corner frequency as that of the jitter transfer function, f-3dB • Trade-off in Loop Bandwidth Setting b/w the i/p Jitter Filtering and Jitter Tolerance CBM Collaboration Meeting, VECC

  16. Low Jitter CDR Architecture I CBM Collaboration Meeting, VECC

  17. Low Jitter CDR Architecture II CBM Collaboration Meeting, VECC

  18. Background – Rad-hard design • Ionizing radiation effects on CMOS ICs: • Total Ionizing Dose (TID) Effects • Issues : threshold-voltage shifts, mobility degradation, and isolation related leakage • Remedy : “Radiation tolerant Layout techniques” – Systematic use of Annular Symmetric Enclosed Layout Transistors (ELT) and p+ guard rings between the n+ diffusions • Single Event Effects (SEE) • Variants: • Non-Destructive : Single Event Upset (SEU), Single Event Transient (DSET) • Destructive : Single Event Latch-Up (SEL) • Issues: • SEU : Depending on the LET, if parasitic charge > node critical charge, a logical switch may occur (bit flip) • DSET : Error rate depends linearly on Clock frequency (glitch) • SEL : Parasitic thyristor structure leading to latch-up • Remedy: • SEU/DSET: Temporal Sampling – Triple Modular Redundancy (TMR), Error Detection and Correction (EDAC);Add Capacitance to sensitive nodes to increase ‘critical charge’ • SEL : Radiation tolerant Layout techniques and usage of p+ guard rings CBM Collaboration Meeting, VECC 14

  19. Background cont ... Rad-hard design • Observations/Experience in CBM Radiation Environment: • TID : • MUCH plane 1 (at 130 cm) : deposited energy (rad/CBM-yr) • at perimeter: ~30krad/yr, in center: ~500krad/yr • Not necessary to have all transistors with ELT layout • SEL: • Not seen as an issue in tests so far in deep submicron CMOS • SEU/SET: • MUCH plane 1 (at 130 cm) : fluence hadron E>20 MeV (/cm2/CBM-yr) • at perimeter: ~2·105 h/cm2/s, at center: ~2·106 h/cm2/s • Hadrons flux VERY Significant for SEUs CBM Collaboration Meeting, VECC 15

  20. Approach: Work Plan • Freeze System level/Interface Specs • Design an appropriate architecture for the High speed Serializer core • Design and Implementation of the Peripheral cores in UMC 180μm process: • CMU • CDR • Serializer and 50 ohm output Impedance driver • Characterization of UMC 0.18μm CMOS process concerning the vulnerability against SEU / SETs • SEU cross section for different High speed Flip-Flop, Multiplexer designs and layouts • Characterization of the critical charge Qcrit /Linear Energy Transfer (LETcrit) • SET sensitivity of the UMC 0.18μm process • Testing : • Functionality/Performance : Design of different Testing/Digital blocks: • Pseudo Random Sequence generator (PRSG) • 8B/10B encoder, FIFOs • FPGA devices to program the Serializer Test Configuration • generation of Test data patterns • monitor PLL’s locking state, etc. • Radiation Tolerance CBM Collaboration Meeting, VECC 16

  21. Approach: Work Plan – Year 1 • Complete literature review and definition of a suitable architecture for the SerDes for operation up to 2.5 Gbps. • Top level modeling of the RF Front end blocks (CMU, CDR) with System level software. • Set up complete process flow for UMC 180 nm CMOS. • Assess the SEU sensitivity of important sub-blocks, including the VCO, PLL loop filter, etc. and identify design criteria, simulation method and means of alleviating the same. • Design/Tape-out (Phase I) of transistor test structures as well as primitives like high speed multiplexers, latches, flip flops with standard and enclosed layouts for technology evaluation and for precise modeling of radiation hard devices. • Complete design, layout and simulation of the CDR and CMU CBM Collaboration Meeting, VECC

  22. Approach: Work Plan – Year 2 • Complete design, layout and simulation of the Serializer core with the 50 ohm output Impedance driver. • Testing for functionality/radiation tolerance for test structures taped out(Phase I). • Tape-out (Phase II) of different CDR/CMU test structures. • Design of appropriate Bias generation schemes and incorporating this in full system simulation. • System integration with proper digital control unit for process compensation and other corrections. • Testing for functionality/radiation tolerance for test structures taped out in Phase II. • Tape-outs (Phase III) for the complete SerDes. • Post Layout simulation and PCB Design of the full system. • Testing for functionality and radiation tolerance for previously taped out system (Phase III). CBM Collaboration Meeting, VECC

  23. Resources Available at AVLSI Lab, IIT KGP CBM Collaboration Meeting, VECC 21

  24. Budget Details for Different Overhead - I CBM Collaboration Meeting, VECC 21

  25. Budget Details for Equipments Required-II CBM Collaboration Meeting, VECC

  26. CBM Collaboration Meeting, VECC 17

  27. CBM Collaboration Meeting, VECC 18

  28. CBM Collaboration Meeting, VECC 19

  29. CBM Collaboration Meeting, VECC 20

  30. THANK YOU FOR YOUR ATTENTION CBM Collaboration Meeting, VECC 22

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