CMOS VLSI DESIGN

1. CMOS VLSI DESIGN Kasin Vichienchom kvkasin@kmitl.ac.th Lecture#4

2. Static Complementary MOS Circuits • Structure of CMOS • CMOS Gates and Layout • Delay • Power Dissipation

3. CMOS Power Consumption Power is drawn from a voltage source attached to the VDD pin(s) of a chip. • Instantaneous Power: • Energy: • Average Power:

4. CMOS Power Consumption • Dynamic Power Consumption • charge and discharge capacitors • Short Circuit Current • short-circuit current path between supply rails during switching • Leakage • Leaking diodes and transistor

5. Dynamic Power Consumption • Dynamic power is required to charge and discharge load capacitances when transistors switch. • One cycle involves a rising and falling output. • On rising output, charge Q = CΔV = CLVDD is required. • On falling output, charge is dumped to GND.

6. Dynamic Power Consumption • Assume that one cycle of charge-discharge completes in one clock peroid TCLK i.e. VIN is the CLK: • Do not depend on RN and RPNot a function of transistor size

7. Dynamic Power Consumption • Practically, CMOS circuits do not switch every clock cycle • If it switches in every n clock cycles then probability of switching in one clock clycle orActivity Factor:α= T/n

8. Dynamic Power Consumption Capacitance seen by output: fF in DSM Supply voltage: decreasing Activity Factor: How often does output switch. Typical value 0.1- 0.2 Clock frequency: increasing

9. CMOS Power Consumption • Dynamic Power Consumption • charge and discharge capacitors • Short Circuit Current • short-circuit current path between supply rails during switching • Leakage • Leaking diodes and transistor

10. Short Circuit Power Consumption • Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting. ISC is also called crowbar current

11. Short Circuit Power Consumption • Function of duration and slope of input signal, tsc • Ipeak determined by the saturation current of the P and N transistors which depend on their sizes • Strong function of the ratio between input and output slopes which is a function of CL • < 10% of dynamic power if rise/fall times are comparable for input and output

12. Example: Power Consumption Example: A typical CMOS inverter in DSM clocked at f = 250 MHZ has CL = 50 fF and use VDD = 1.8V P = αCV2f = (50fF)(1.8)2(250MHZ) = 40.5 µW Example:20 M logic transistors chip, average width: 12λ VDD=1.2 V , use 0.1 µm process Cg = 2 fF/mm, activity factor = 0.1

13. CMOS Power Consumption • Dynamic Power Consumption • charge and discharge capacitors • Short Circuit Current • short-circuit current path between supply rails during switching • Leakage • Leaking diodes and transistor

14. Gate Leakage Leakage Power Consumption • I diode = Js x area where Js ≈ 10 – 100 pA/µm2 @ 25ºC for 0.25µm process and double every 9º C • Isub ≈ pA -µA depending on slop factor: 60 – 100 mV/dec • Gate leakage ≈ nA/µm for thin oxide, pA/µm for thick oxide

15. Low Power Design • Power = Dynamic (%85) + Short Circuit(%7) + Leak (%8) Trend: • Reduce dynamic power • α: sleep mode • C: small transistors (esp. on clock), short wires • VDD: lowest suitable voltage • f: lowest suitable frequency • Reduce static power • Selectively use low Vt devices • Leakage reduction: reduce physical capacitance

16. Logic Styles • Static CMOS Logic • Dynamic CMOS Logic • Domino Logic • np-CMOS(Zipper) • Alternative Logic Styles • Ratioed Logic • Pass Transistor Logic • Differential Cascode Voltage Swing Logic

17. Dynamic CMOS Circuits • In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. • fan-in of n requires 2n (n N-type + n P-type) devices • Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. • requires on n + 2 (n+1 N-type + 1 P-type) transistors

18. Mp Dynamic Circuits Static CMOS Dynamic CMOS VDD Clk In1 PMOS only In2 PUN Out … InN In1 CL F(In1,In2,…InN) In2 PDN … In1 InN In2 PDN … NMOS only InN Me Clk

19. Mp Mp ((AB)+C) Dynamic CMOS Circuits Operation Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) off Clk on Clk 1 Out Out In1 CL A In2 PDN C … InN B Me Clk off Me Clk on

20. Dynamic CMOS Circuits Conditions on output • Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. • Inputs to the gate can make at most one transition during evaluation. • Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL Source : Jan Rabaey

21. Dynamic CMOS Circuits Properties of Dynamic Gates • Logic function is implemented by the PDN only • number of transistors is N + 2 (versus 2N for static complementary CMOS) • Full swing outputs (VOL = GND and VOH = VDD) • Non-ratioed - sizing of the devices does not affect the logic levels • Faster switching speeds • reduced load capacitance due to lower input capacitance (Cin) • reduced load capacitance due to smaller output loading (Cout) • no Isc, so all the current provided by PDN goes into discharging CL Source : Jan Rabaey

22. Dynamic CMOS Circuits Properties of Dynamic Gates • Overall power dissipation usually higher than static CMOS • no static current path ever exists between VDD and GND (including Psc) • no glitching • higher transition probabilities • extra load on Clk • PDN starts to work as soon as the input signals exceed VTn, so VSW, VIH and VIL equal to VTn • low noise margin low (NML) • Needs a precharge/evaluate clock Source : Jan Rabaey

23. Dynamic CMOS Circuits Signal Integrity Issues in Dynamic CMOS gate design • Charge Leakage • Charge Sharing • Capacitive Coupling • Clock Feedthrough

24. Mp CL Charge Leakage CLK Clk (2) Out (1) A Evaluate VOut Clk Me Precharge Leakage sources • Charge gradually leaks away due to leakage currents eventually resulting in malfunctioning of the gate • Sub-threshold leak (most dominant) • Reverse-biased diode leak Source : Jan Rabaey

25. Charge Leakage • Output settles to an intermediate voltage determined by a resistive divider of the pull-up and pull-down networks • Once the output drops below the switching threshold of the fan-out logic gate, the output is interpreted as a low voltage. Source : Jan Rabaey

26. CL CL Charge Leakage Solution : Bleeder Transistor Bleeder Bleeder Clk Mp Mbp Clk Mp Mbp Out A A Out B B Me Me Clk Clk • Bleeder device is kept small to have high resistance • Usually implemented in a feedback configuration to eliminate the static power dissipation Source : Jan Rabaey

27. CL CA CB Charge Sharing Clk Mp Assume that all inputs are set to 0 during precharge, and that the capacitance CA is discharged. Later input A makes a 0 =>1 turning Ma on. Charge stored originally on CL is redistributed (shared) over CA Out A Ma B=0 Clk Me • Charge sharing causes a drop in the output voltage, which can not be recovered due to the dynamic nature of the circuit.

28. Clk Mp Out A B=0 CL CA CB Clk Me Charge Sharing • Causes leakage current in INV if ΔV <|VTP| • Causes wrong output if Vout < VSW

29. CL=50fF Cd=10fF Cb=15fF Cc=15fF Ca=15fF Charge Sharing Can you calculate ΔV ? Clk Out A A B B B B C C Clk ∆Vout = VDD ((Ca + Cc)/((Ca + Cc) + CL)) Source : Jan Rabaey

30. Charge Sharing Solution Clk Clk Mp Mkp Out A B Me Clk • Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) Source : Jan Rabaey

31. CL1 CL2 Voltage Out1 Clk Out2 In Time, ns Capacitive Coupling • Relative high impedance of the output node makes the circuit very sensitive to crosstalk effects. Clk Mp =1 Out1 Out2 =0 In A=0 B=0 Backgate coupling effect Clk Me Static NAND Dynamic NAND Source : Jan Rabaey

32. CL Clock Feedthrough • The fast rising (and falling edges) of the clock couple to Out. Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. • May causes drain-body diode to become forward biased Clock feedthrough Clk Mp Out Voltage A A,B & Clk Out B Clk Me Time, ns Clock feedthrough Source : Jan Rabaey

33. Clk In VTn Out1 V Out2 Cascading Dynamic Circuits V Clk Clk Mp Mp Out1 Out2 In1 M1 Input 0 1 is allowed Clk Me In2 Input 1 0 causes a degrade output Clk Me Out2 stops discharging when Out1 reaches VTnof M1 t • Correct operation is guaranteed as long as theinputs can only make a single 0  1 transitions during the evaluation period Source : Jan Rabaey

34. Domino Logic • The cascading of dynamic gates with an inverter inserted in between. • All the inputs are set to 0 at the end of precharge phase. Thus only transitions during evaluation phase are 0  1 • Only non-inverting logic can be implemented Mbp Clk Mp Clk Mp Out1 Out2 1  1 1  0 0  0 0  1 In1 In4 PDN In2 PDN In5 In3 Clk Me Clk Me Source : Jan Rabaey

35. Clk Ini Ini Ini Ini PDN PDN PDN PDN Inj Inj Inj Inj Clk Domino Logic • All the gates are precharged in parallel then sequentially evaluated like falling dominos • Very high speed can be achieved • only rising edge delay exists ( tPHL = 0 ) • The inverter also • increases noise immunity • can be used to drive a bleeder device Source : Jan Rabaey

36. Domino Logic Example: A 4-bit Dynamic Comparator • if A3-A0 = B3-B0; then Out = 0 Source: Banar

37. np-CMOS (Zipper) Clk Me Clk Mp Out1 1  1 1  0 In4 PUN In1 In5 In2 PDN 0  0 0  1 In3 Out2 (to PDN) Clk Mp Clk Me • Eliminate need of the static inverter • Only 0  1 transitions allowed at inputs of PDN • Only 1  0 transitions allowed at inputs of PUN • PUN is slower than PDN. To equalize the delays requires extra area • Need both Clk and Clk Source : Jan Rabaey

38. Differential (Dual-Rail) Domino Logic • Inverting and non-inverting inputs/output • Widely used in high-performance microprocessors With keeper Devices Source: Hodges

39. Logic Styles • Static CMOS Logic • Dynamic CMOS Logic • Domino Logic • np-CMOS(Zipper) • Alternative Logic Styles • Ratioed Logic • Differential Cascode Voltage Swing Logic • Pass Transistor Logic

40. V V V DD DD DD Resistive In PMOS 1 Load In R PUN Load 2 L L In 3 V SS F F F In In In 1 1 1 In In In PDN PDN PDN 2 2 2 In In In 3 3 3 V V V SS SS SS (a) resistive load (b) pseudo-NMOS (a) CMOS Ratioed Logic • Reduce the number of devices over complementary CMOS Source : Jan Rabaey

41. Pseudo-NMOS Example 8-input NAND Istanding • Replace eight PMOS connected in series with a PMOS • Smaller area and load but more power dissipation due to standing current when output is low since PMOS is always on • VOH = VDD but VOL > GND Source: Hodges

42. Differential Cascode Voltage Switching Logic • DCVS or CVSL • true and complementary input/output • one of PDN will be ON the other OFF • ratioed circuits without static power consumption • faster than regular static CMOS circuit Source: Weste

43. CVSL Example 4-input XOR share transistor Source: Weste

44. Pass Transistor Logic B A Out Out Switch s t B u p Network B n I • Structure • switch can be either NMOS/PMOS • primary inputs drive not only Gate but Drain/Source as well • N transistors instead of 2N • no static power consumption

45. B A B F = AB 0 Pass Transistor Logic (PTL) Example: 2-input AND NMOS Pass Logic • Gate is static because a low-impedance path exists to both supply rails under all circumstances • Bidirectional

46. NMOS PT • Vx does not pull up to VDD, but VDD – VTn • threshold voltage drop causes static power dissipation i.e. M2 may be weakly conducting forming a path from VDD to GND • same situation when use PMOS only pass transistor Source : Jan Rabaey

47. Symbol C=VDD C=GND A=VDD A=GND C=GND C=VDD Transmission Gate (TG) • Full swing bidirectional switch controlled by the gate signal C, A = B if C=1 • Also called ‘Analog Switch’

48. Transmission Gate • Example • 2:1 Multiplexer • XOR and XNOR Gate Source: Hodges

49. Transmission Gate 4:1 Multiplexer Single-level Mux Two-level Mux Source: Hodges

50. Transmission Gate • How to Implement Logic Function using TG • Select control signals and build a truth for all possible combinations • Use Multiplexer-design style • OR Operation => Parallel TG; AND Operation => Series TG