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Jet algorithm / FPGA

Jet algorithm / FPGA. by Attila Hidvégi Stockholm University. Content. Problems found and fixed Subject to debate Status / Outlook. Problems found and fixed. FIO FFs incorrectly implemented after clocking scheme changes Not located in IOB Reduced working FIO window

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Jet algorithm / FPGA

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  1. Jet algorithm / FPGA by Attila Hidvégi Stockholm University

  2. Content • Problems found and fixed • Subject to debate • Status / Outlook

  3. Problems found and fixed • FIO FFs incorrectly implemented after clocking scheme changes • Not located in IOB • Reduced working FIO window • Caused by a resource limitation in the Virtex-II IOBs • It is fixed now • VME communication might be lost at a specific (narrow) clk_des2 setting • Will be investigated and probably fixed… • …but since it is located in a non working FIO region anyway, it is on low priority

  4. Subject to debate • Should the production version of the jet-FPGA include hardware support for fast delay scan of the FIOs? • No • FPGA size limitation (the jet algorithm had to be removed for a good reason in the special test version) • Timing constraints may be pushed beyond the limits • The relative phase between clk_des1 and clk_des2 should be constant for a properly working JEM, hence no need for frequent delay scans • What’s so hurry? • Spy memories should be used for delay scan • They exist in all version and the delay scan could be firmware version independent. (Right now it relies on a firmware which will not be maintained.) • Old version of the software exist which could be updated easily • Yes • …

  5. Status / Outlook • Update the JEM specification about clocking scheme. • Will be done in the near future. • FCAL mapping still needs to be verified. (I think…) • FIO FFs issue resolved. • Working window of clk_des2 for the inputs has been determined. • Maintenance…

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