FPGA Two Day Advanced FPGA Workshop Instructors

1. FPGA Two Day Advanced FPGA WorkshopInstructors Craig Kief Deputy Director, COSMIAC craig.kief@cosmiac.org Karl Henry Instructor, JF Drake State Karl.Henry@DrakeState.edu Bassam Matar Instructor, Chandler-Gilbert b.matar@cgcmail.maricopa.edu Brian Zufelt Engineer, COSMIAC Brian.zufelt@cosmiac.org Ui Luu Instructor, Glendale ui.luu@gcmail.maricopa.edu Pete Lomeli Instructor, Central Arizona Pete.Lomeli@centralaz.edu 1

2. Introductions • Who are you? • Where are you from? • What do you want to learn from this? • Where are the objectives?

3. Labs we will cover • Spin up • Counter • Testbench • FSM • Seq Det • IP Cores

4. Why we are here again

5. Method: Immersive hands-on design for every student Students learn more, faster, and better with unrestricted access to design tools… …overall learning improves when applied design skills taught early; …overall performance improves when design skills used frequently; …and they like it* *results published in 2008 and 2009 ASEE proceedings I never teach my pupils; I only attempt to provide the conditions in which they can learn. Albert Einstein

6. Technology keeps moving forward faster – get on the train or be left behind • In a meeting the first week in June, Xilinx announced the following: • The new Virtex 7 devices use approximately 20 watts • They are actually four chips on a single chip connected with an interposer • The contain approximately 6.8 billion transistors

7. Low-cost kits and Free CAD toolsfor every engineering student Terasic DE0 Altera Cyclone III $79 Digilent Basys2 Xilinx Spartan 3E $59 Digilent Nexys2 Xilinx Spartan 3E $99 Terasic DE1 Altera Cyclone II $125 • No Lab Required! Students work on real designs at a time and place of their choosing

8. FPGA’s Across the Curriculum

9. Please interrupt and ask questions

10. Overview • All Xilinx FPGAs contain the same basic resources • Logic Resources • Slices (grouped into CLBs) • Contain combinatorial logic and register resources • Memory • Multipliers • Interconnect Resources • Programmable interconnect • IOBs • Interface between the FPGA and the outside world • Other resources • Global clock buffers • Boundary scan logic

11. What makes up an FPGA? Simplified Slice Structure Slice 0 LUT PRE Carry D Q CE CLR • Groups of Slices make up a Complex Logic Block (CLB) • Each slice has four outputs • Two registered outputs, two non-registered outputs LUT Carry PRE D Q CE CLR

12. Spartan-3E Architecture CLB Slice

13. DESIGN Hardware Descriptive Languages (HDL) VHDL VERILOG C++ SYSGEN Schematic Capture EDK IP Cores Limitless Tools SYNTHESIS Many files in – one file out One File = EDIF Syntax Checking Less Tool Choices IMPLEMENTATION PLACE AND ROUTE Place Logic onto the CLBs Route IOB CLB IOB UCF EDIF .BIT ONE TOOL PROGRAM JTAG PROGRAM FPGA PROM ADEPT vs JTAG Chain BEHAVIORAL SIMULATION TIMING SIMULATION

14. Design

15. How are FPGA projects Designed? • There are many different methodolgies for programming (or designing) with FPGAs • Hardware Descriptive Language (HDL) • VHDL • Verilog • Schematic Capture • C Code • EDK • System Generator

16. VHDL Code The title of the article is "Analysis of the programmable logic usage and assurace survey results“ revision 10.1, sept 25,2002Glenn research center, Cleveland, Ohio.Quote:It is a serious mistake to equate VHDL programming to software. At best it is firmware, but for the most part there isn't a good name for programming FPGA logic. In a high performance design like ours, the minute you forget that you are designing hardware and think you are writing software, you fail.

17. VHDL Code Forest Level View

18. Architecture Declaration

19. VHDL Recap and Objects

20. Variables

21. Not limitless Operators

22. Available Operators

23. Picking off bits

24. Data types, operators and conversion

25. CASE STATEMENT 00 01 10 11 • SELECTED SIGNAL ASSIGNMENT SELECT X WHEN “00”, Y WHEN “01”, Z WHEN “10”, Z WHEN “OTHERS”; * USED WHEN NO PRIORITY EQUIVALENT TO CASE STATEMENT (get code)

26. IF STATEMENT X 0 1 Y OUT 0 1 A Z B • CONDITIONAL SIGNAL ASSIGNMENT • PROCESS (X, Y, Z, A, B) • SENSITIVITY LIST. ANYTHING READ MUST BE HERE NOTHING HERE IS EVER ON LEFT SIDE OF ASSIGNMENT – Everything on Right hand side of assignment is read IF B = ‘1’ THEN OUT <= Z ELSIF A = ‘1’ OUT <= Y ELSE OUT <= X END IF END PROCESS * PRIORITY EXISTS

27. Assignment Operators • <= Used to assign a value to a SIGNAL • a <= ‘1’; • := Used to assign an value to a VARIABLE, CONSTANT, or GENERIC. Used also for establishing initial values • constant N: integer:=18; • => Used to assign values to individual vector elements or with OTHERS • display_out : display_controller • port map( • clk => clk, • reset => reset, • q_reg <= (others=>'0');

28. RULES DON’T USE PROCESS IF DON’T HAVE TO – Simple, concurrent and selected signal assignments can be done outside of a process. Danger of using a process is you might get a inferred latch (unwanted clock cycle) MULTIPLE ASSIGNMENTS TO SAME SIGNAL, LAST ONE HOLDS FOR EVERY OUTPUT SIGNAL THAT CAN BE ASSIGNED, ALL POSSIBLE CONDITIONS MUST BE ADDRESSED– Always assign default values at the top of the block before case and if statements ALL INPUT SIGNALS READ MUST BE IN THE SENSITIVITY LIST FOR COMBINATIONAL LOGIC FOR SEQUENTIAL USE CLK/RESET

29. I wish to help all of you to begin teaching FPGAs

30. Start the Learning The key from this workshop is to learn what you need to know to successfully teach with FPGAs

31. Get Started! Create a 2 input AND gate! Create the VHDL, Testbench, UCF and download it Steps: • Start ISE • New Source – VHDL Module • Use Wizard to do I/O • New Source – Create UCF for pin assignment • New Source – VHDL Testbench • Simulate • Program FPGA

32. Things to discuss before the labs • Slow clock • Using it, changing it for simulations • Debouncing • Alex material • ISE 7 vs 14

33. Labs we will cover • Spin up • Counter • Testbench • FSM • Seq Det • IP Cores

34. Lab 6 - Counters • Download ISE 14.1 version of Lab 6 from http://cosmiac.org/Projects_FPGA.html • Create New Project • Add Source Files: • counter.vhd • display_controller.vhd • counter_TB.vhd • counter4.ucf • Download and Review FPGA Reference Manual • Change clk pin assignment as needed • Change UCF pin assignments as needed • Review vhd and ucf code • Review Testbench

35. Counters - Eloquent Example

36. Counter

37. Counter – cont. (2)

38. Counter – cont. (3)

39. Display_Controller

40. Display_Controller – cont. (2)

41. Display_Controller – cont. (3)

42. UCF – Spartan 6 pins We are using a Nexys 2, Spartan-3 for this class. We will need to change the pin assignments using the diagram.

43. Labs we will cover • Spin up • Counter • Testbench • FSM • Seq Det • IP Cores

44. Autogenerated Test Benches • Build a module test a module, …., build a system of modules and test the system • Excellent job for technician or junior engineer • Creating the framework of the test bench is easy and painless • Need to have directory of files and test benches and need to be able to quickly pick them out and mate the source file to its test file

45. Counter Test Bench - 1

46. Counter Test Bench - 2

47. Counter Test Bench - 3

48. Counter Test Bench - 4

49. Labs we will cover • Spin up • Counter • Testbench • FSM • Seq Det • IP Cores

50. LAB 10Finite State Machine (FSM) Ui Luu Glendale Community College Bassam Matar Chandler-Gilbert Community College