Course Agenda

1. Course Agenda DSP Design Flow

2. Objectives After completing this course, you will be able to: • Describe the different design flows for implementing DSP functions, with a large focus on the System Generator • Understand the Xilinx FPGA capabilities and know how to implement a design from algorithm concept to hardware simulation • Perform Hardware in the Loop and HDL co-simulations and improve productivity

3. Day 1 • Introduction • Power of Parallelism • Platform FPGA Virtex-II/ Virtex-II Pro Series • Spartan-3 Architecture • DSP Design Flows in FPGA • Using VHDL • Using the Xilinx CORE Generator • Using the Xilinx System Generator for DSP • Hardware in the Loop Accelerated Verification

4. Day 2 • Digital Filtering • Digital Filtering Blocks • Use the FDA Tool in Conjunction with the Xilinx Blockset • HDL Co-Simulation • Concept • Supporting Blocks • Co-Simulation Procedure

5. Day 2 • Looking Under the Hood • Quantization and Overflow • Hardware Cost • Data Path Management • Controlling the System • Control Mechanism • Control Blocks • Multi-rate Systems • Sample Rates • Sample Rate Changing Blocks • Hardware Realization of Sample Rate Changing Blocks

6. Bonus Material • Advanced Features • Multiple FPGAs • Multiple System Generator versions • PicoBlaze microcontroller • User IP Library • Parametric Design Techniques