Design and Implementation of VLSI Systems (EN0160) Lecture 20: Circuit Design Pitfalls

Design and Implementation of VLSI Systems (EN0160) Lecture 20: Circuit Design Pitfalls Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

Underestimating different phenomena Variations Process or runtime Reliability concerns • Design for the best and worst and the unexpected in the future! How can circuit design go wrong? [material from subsection 4.7, 4.8 and 6.3]

Principle: Leakage • Eventually subthreshold leakage may disturb charge • Solution: Staticize node with feedback • Or periodically refresh node (requires fast clock, not practical processes with big leakage) Pitfall 1: Underestimating Leakage • Circuit • Latch • Symptom • Load a 0 into Q • Set f = 0 • Eventually Q spontaneously flips to 1

Circuit Pseudo-nMOS OR Pitfall 2: Underestimating contention due to transistor ratios • Symptom • When only one input is true, Y = 0. • Perhaps only happens in SF corner. • Principle: Ratio Failure • nMOS and pMOS fight each other. • If the pMOS is too strong, nMOS cannot pull X low enough. • Solution: Check that ratio is satisfied in all corners

Principle: Charge Sharing • If X was low, it shares charge with Y • Solutions: Limit charge sharing • Safe if CY >> CX • Or precharge node X too Pitfall 3: Underestimating charge sharing • Circuit • Domino AND gate • Symptom • Precharge gate while A = B = 0, so Z = 0 • Set f = 1 • A rises • Z is observed to sometimes rise • Principle: • Solutions:

Pitfall 4: ignoring process variations Both MOSFETs have 30nm channel with 130 dopant atoms in the channel depletion region threshold voltage 0.97V threshold voltage 0.57V [source: Asenov’99] Variations are mostly pronounced in gate length, threshold voltage, and oxide thickness

[source: Devgan’05] 1st CPU 2nd CPU Power 4 server chip thermal profile during runtime cache Pitfall 5: ignoring runtime variations (temperature)

Pitfall 5: ignoring runtime variations (IR drop) • IR drop/bumps in power supply network reduces saturation current  larger transistor delay • (deviations in VDD can be by up to 10%)

Electromigration: “Electron wind” causes movement of metal atoms along wires Excessive electromigration leads to open circuits Most significant for unidirectional (DC) current: depends on current density Jdc (current / area) • Hot Carriers: Electric fields across channel impart high energies to some carriers • “hot” carriers blasted into the gate oxide become trapped • → causes shift in Vt over time • →Eventually Vt shifts too far for devices to operate correctly Pitfall 6: ignoring the future (reliability concerns)

Transistors have uncertainty in parameters Process: Leff, Vt, tox of nMOS and pMOS Vary around typical (T) values Fast (F) Leff: ______ Vt: ______ tox: ______ Slow (S): opposite Not all parameters are independent for nMOS and pMOS Combat variability by designing your system in different “corners” short low thin

VDD and T also vary in time and space Fast: VDD: ____ T: ____ high low Corners for runtime variations

Process corners describe worst case variations If a design works in all corners, it will probably work for any variation. Describe corner with four letters (T, F, S) nMOS speed pMOS speed Voltage Temperature Process corners

Some critical simulation corners include Simulate your design at different corners

Design and Implementation of VLSI Systems (EN0160) Lecture 20: Circuit Design Pitfalls