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Chapter Four

Chapter Four. Register Transfer and Micro operations. Contents. 4-1 Register Transfer Language. 4-2 Register Transfer. 4-3 Bus and Memory transfers. 4-4 Arithmetic Micro operations. 4-5 Logic Micro operations.

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Chapter Four

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  1. Chapter Four Register Transfer and Micro operations

  2. Contents • 4-1 Register Transfer Language • 4-2 Register Transfer • 4-3 Bus and Memory transfers • 4-4 Arithmetic Micro operations • 4-5 Logic Micro operations • 4-6 Shift Micro operations • 4-7 Arithmetic logic shift unit

  3. Register Transfer Language The set of register it contains and their functions. The sequence of micro operations performed on the binary information stored in the register. The control that initiated the sequence of micro operations.

  4. Figure 4-1Block diagram of register R1 7 6 5 4 3 2 1 0 Register R Showing individual bits 15 0 15 8 7 0 R2 PC(H) PC(L) Numbering of bits Divide into two parts

  5. Figure 4-2Transfer from R1 to R2 P: R2 R1 Control circuit Load P Clock R2 n R1

  6. Figure 4-2 bTiming diagram t t+1 Clock load Transfer occurs here

  7. Table 4-1Basic symbols for register transfer Symbol Description Examples Letters (and numerals) Denotes a register MAR, R2 Parentheses ( ) Denotes a part of a register R2(0-7),R2(L) Arrow Denotes transfer of information R2 R1 Comma , Separates two micro operations R2 R1, R1 R2

  8. Figure 4-3BUS AND MEMORY TRANSFER 4 – L I N E C O M M O N B U S S1 S0 4 x 1 M U X 3 3 2 1 0 4 x 1 M U X 2 3 2 1 0 4 x 1 M U X 1 3 2 1 0 4 x 1 M U X 0 3 2 1 0 D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0 D2 D1D0 C2 C1C0 B2 B1B0 A2 A1A0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 REGISTER D REGISTER C REGISTER B REGISTER A

  9. Table 4-2Function table for bus

  10. Figure 4-4Graphical symbol for Three-state Bus Buffers

  11. Figure 4-5Bus line with three state-buffers Bus line for bit 0 A0 B0 C0 D0 0 S0 1 2 x 4 Decoder Select S0 2 Enable E 3

  12. Memory Transfer Read: DR M[AR] Write: M[AR] R1

  13. Arithmetic Micro operations Register transfer micro operations transfer binary information from one register to another. Arithmetic micro operation performs arithmetic operations on numeric data stored in register. Logic micro operations perform bit manipulation operations on nonnumeric data stored in register. Shift micro operations perform shift operations on data stored register.

  14. Table 4-3Arithmetic Micro operation Symbolic designation Description R3 R1+ R2 Contents of R1 plus R2 transferred to R3 R3 R1- R2 Contents of R1 minus R2 transferred to R3 R2 R2 Complement the contents of R2( 1’s complement) R2 R2 + 1 2’s complement the contents of R2(negate) R3  R1+ R2 + 1 R1 plus the2’s complement of R2(subtraction) R1 R1 + 1 Increment the contents of R1 by one R1 R1 - 1 Decrement the contents of R1 by one

  15. Figure 4-64 – Bit binary adder B1 A0 B3 A3 B2 A2 A1 B0 C3 C0 C2 C1 FA FA FA FA C4 S3 S2 S1 S0

  16. Figure 4-74 – bit adder subtractor B1 A0 B3 A3 B2 A2 A1 B0 M C0 C3 C2 C1 FA FA FA FA C4 S3 S1 S0 S2

  17. Figure 4-84 – Bit binary Incrementer A0 1 A3 A2 A1 x y x y x y x y HA HA HA HA C S C S C S C S C4 S3 S2 S0 S1

  18. Figure 4-9 4-bit arithmetic circuit Cin S0 S1 Xo Co A0 S1 Do S0 4 x 1 MUX B0 0 1 yo C1 2 3 X1 C1 S1 D1 S0 4 x 1 MUX B1 0 y1 C2 1 2 3 X2 C2 D2 S1 S0 B2 4 x 1 MUX 0 y2 C3 1 2 3 X3 C3 D3 S1 S0 4 x 1 MUX B3 y3 C4 0 1 2 Cout 3 0 1

  19. Table 4-4Arithmetic circuit function table Select Input Output Micro operation D = A + Y +Cin S1 S0 Cin Y 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 B B B B 0 0 1 1 D = A + B D = A + B + 1 D = A + B D = A + B + 1 D = A D = A + 1 D = A - 1 D = A Add Add with carry Subt. with borrow Subtract Transfer A Increment A Decrement A Transfer A

  20. Table 4 – 5Truth table for 16 Function of two variables x y F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1

  21. TABLE 4-6SIXTEEN LOGIC MICRO OPERATIONS Boolean function Micro operations Name F0 = 0 F  0 Clear F1 = xy FA ^ B And F2 = xy’ FA ^ B F3 = x FA Transfer A F4 = x’y FA ^ B F5 = y F B Transfer B F6 = x y F A B Exclusive-or F7 = x + y F A ٧ B OR F8 = (x + Y)’ F  A V B NOR F9 = (x Y)’ F A B Exclusive-NOR F10 = y’ F B Complement B F11 = x + y ‘ F A V B F12 = x’ F A Complement A F13 = x’ + y F  A v B F14 = (xy)’ F  A ^ B NAND F15 = 1 F  all 1’s Set to all 1’s

  22. Figure 4-10One stage of logic circuit S1 4x1 MUX S0 S1 S0 Output Operation A i 0 B i 0 0 1 1 0 1 0 1 E = A ^ B AND 1 E = A v B OR E i E = A B XOR 2 E = A COMPLEMENT 3

  23. Figure 4-124-bit combinational circuit shifter Select 0 for shift right 1 for shift left Serial input (IR) S Mux H0 0 1 Ao Select S Output A1 S H1 H2 H3 H0 Mux H1 0 1 A3 0 1 IR A1 A0 A2 A1 A3 A2 Il A4 S Mux H2 0 1 S H3 Mux 0 1 Serial input (IL)

  24. Figure 4-13One stage of arithmetic logic shift unit S3 S2 Ci S1 S0 Di One stage of arithmetic circuit Select 0 1 2 3 4 x 1 MUX Ci+1 F i Ei One stage of logic circuit Bi Ai shr Ai -1 Ai+1 shl

  25. Table 4-8 Function table for arithmetic logic shift unit Operation Select Operation Function S1 Cin S3 S2 S0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 x x 0 0 1 1 0 0 1 1 0 1 0 1 x x 0 1 0 1 0 1 0 1 x x x x x x F = A F = A + 1 F = A + B F = A + B +1 F = A + B F = A + B + 1 F = A -1 F = A F = A ^ B F = A v B F = A B F = A F = shr A R = shl A Transfer A Increment A Addition Add with carry Subtract with borrow Subtraction Decrement A Transfer A AND OR XOR Complement A Shift right A into F Shift left A into F

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