Toward Verification Closure from industrial perspective

1. Toward Verification Closure from industrial perspective Yu-Chin Hsu Vice President, R&D, Logic Verification Group

2. Simulators Prototypes DFD Emulators Growing Trends • Exploding Size • Growing Complexity • Unfamiliar IP • 30B Xtor’s theoretically possible in 20~30nm technology today Signal Data

3. EDA Market * Courtesy Gary Smith EDA 5

4. Concept Architecture Implementation Integration Fab Platformintegration Implementation and Verification Firmware design & verification Application software design & Verification Systemspec Architecturedesign & verification SystemValidation Block design& verification Chip design,Integration &Verification Siliconfabrication&Test Time in Weeks Silicon Requirements Final RTL Early RTL HDD Tapeout Design levels System RTL/Gate prototype

5. Drivers to Cope with Complexity • Methodology evolution • Parallelism consideration – multi-core • Multi-facet consideration – power, performance, visibility, etc. • Methodology revolution • Platform design -- Domain specific customization • ESL -- Raise the abstraction level to behavior level Typical Design Process Production Release New SoC Design & Verification Process Production Release

6. Methodology Moved to Handle Complexity Standardization FPGA Platform customization Makimoto’s Wave • Platforms – Most popular design methodology today! • Today most platforms are targeted at single customers and applications • Software is an important part of the platform • Abstract away the hardware • Enable the easy deployment of the platform • Tools are important in platform deployment • Do not need to be as general purpose • More specialized tasks

7. Platform-based Design • Central notions • A regular pre-verified collection of IP blocks • Usually customized for specific application domains • One stop shopping for IP • A way to sell silicon • Also means locking a customer in • Think TSMC and the design services around • Industry disaggregating • Think Nokia • Nokia would rather not be a hardware company • Nokia is a software, design and marketing company • TI is the hardware designer for Nokia • Helps Nokia lower costs and focus efforts • Nokia wants to know that their application runs on the platform – efficiently and effectively

8. However…Something Doesn’t Happen As We Thought • Early ESL attempts failed because they did not target: • The right person • The right starting point • The right objectives • I still don’t think we have a clear picture today • Although it is emerging • Productivity is THE primary driver • Adoption constrained by lack of models

9. RTL Simulation Is Still in the Center • However, the execution time IS CONCERN! • Technologies are added to improve the performance • Parallelism • Visibility enhancement with performance cost reduction • Other technologies usage increasing but not be able to replace or reduce simulation usage in short term • Hardware • Formal HiSilicon Verification Seminar

10. Verification and Closure Debug & Design comprehension Closure loop Improve Coverage Test Bench No Stimulus Assertion Closure ? Verification Plan Coverage Checker Done Verificationmanagement Design Specification Engines Formal Yes Simulation Correctly ? HDL design No Hardware Debug loop

11. Toward Verification Closure • Language Strategy • HDL/HVL trend • Debug loop -- Detect and fix bugs as early as possible • Fast turnaround time on simulation, debug and design fix • Closure loop -- Detect and fix verification holes to sign off RTL verification • Measure and improve the coverage

12. Language Strategy • Simulator – main methodology, commodity • HDL/HVL has merged into one language • SystemC, • e language, • System Verilog – growing • Libraries and methodologies to support testbench development • VMM: initial leading, based on Vera • OVM: rapidly catching up, completely free, and open (based on IEEE 1800-2005)

13. Language Strategy (cont’d) • Assertion language • PSL: based on IBM sugar, focus on procedure assertion • Used mainly by verification engineers • SVA: part of System Verilog, provide both procedure and design assertion • Used by design engineers • Adoption of SVA is accelerating as its strong integration with dynamic verification

14. Debug Loop • Simulator is commodity. Technologies are developed to tackle complexity to improve productivity Visibility Enhancement Debug Diagnosis Simulation The core of logic verification Hardware StaticAnalysis Formal Analysis VerificationIP Formal Verification

15. Formal Verification • Survey in 2007: Does your project use formal "bug hunters"? (of all 818 engineers) • Don't use : ######################## 74.5% • Mentor 0-In : ### 6.5% • Synopsys Magellan : #### 7.9% • Jasper : ## 4.6% • Real Intent Verix : 1.2% • Cadence ISV/IFV/BlackTie : ### 6.21% • IBM RuleBase : # 2.0% • Atrenta Periscope : 0.5% • OneSpin 360MV : 0.8% • According to Gary Smith EDA, formal property checking is used by 65% of chip design companies in 2009

16. Top 3 Use Cases Survey SpringSoft Confidential

17. General Wish List on Formal Typical complaints: Difficult to use, work for small block, false positive • “Bigger, better, faster” technology • Common constraints • Constrained random test-benches vs. formal • Debugging of assertions • When an assertion fails, is this because I didn’t write it properly, or because something happened in the RTL? • Whether you have enough assertions • Make sure there are enough assertions to check everything in your RTL

18. Closure Loop Verification Plan Closure? CoverageProducts simulator T1 T2 … Tn Testbench Formal Verification VIP coverage Functional coverage Assertion coverage FunctionalQualification DUV Code coverage Mutation coverage Emulation

19. Coverage Data • Code Coverage • Block, Branch, Expression, FSM Coverage • Functional Coverage • Coverage of variable values, binning, specification of sampling, and cross products • Mutation-based Coverage • How robust is your testbench environment • Assertion Coverage • Assertion formally covered • Assertion dynamically covered

20. UCIS High-Level Goals • UCIS = Unified Coverage Interoperability Standard • Start with standard terminology definition. • API design spec draft is available for accessing unified coverage database (UCDB). • Database is the repository of all coverage information. • Interoperability standardization is on API, not DB implementation. • API supports fast read, write and read-modify-write. • Support merging data and reporting data usage model. • *From UCIS API design spec draft

21. Hard Verification Closure Decision • What needs to be covered? • What has been covered? • How to improve the coverage? • How long before we are done?

22. Closure Loop • Relatively fewer successful commercial tools in the closure loop. Anything improve coverage is helpful. Monitor Results Verification-Plan Prepare TB Run Simulation Global view of verification items • Itemize what needed to be tested ? • How to test them? • How critical are they? Global view of verification status • What are missing? • How critical are they in the picture? • How to interpret these issues? Coverage convergence

23. The Light and the Dark of Moore’s Law Smaller Geometries  SoC-Scale Chips Amazing Electronic Tools and Toys Today’s Chips are Big and Rich! Enormous Complexity Too Much Data  Overwhelming Detail

24. Summary: Big and Rich Design VERIFICATION Closure Build