Reconfigurable Hardware Scheduler for RTS

1. Reconfigurable Hardware Scheduler for RTS Chad Nelson, Brian Peck, Chetan Kumar N G

2. Motivation Scheduling overhead has been a major limiting factor in the implementation of dynamic priority scheduling algorithms in Real Time Application. Overhead due to: • Time-tick processing • Runtime priority calculation • Context Switching Solution: Build the scheduler in hardware • ASIC implementation is not flexible and difficult to modify.

3. Project Proposal To build Reconfigurable Hardware Scheduler to support multiple scheduling disciplines(EDF and RM) and make it runtime reconfigurable. Platform/Tools Xilinx Virtex-5 FXT FPGA ML507 Evaluation Platform, Xilinx ISE, Modelsim Advantages: • Minimizes processor time wasted by scheduler • Reduce time-tick processing overhead • Provides accurate timing • Task sets can be modified during runtime • Supports multiple scheduling algorithms

4. High Level Design Clock Runtime Controller Current Task Processor CPU Interface Task Table Ready Queue Sleep Queue

5. Priority Queue Cell Task Register Comparator Multiplexor Data from Left Cell Data from Right Cell New Data

6. Task Registers Block RAM (Indexed by Task ID) Ready Queue and Current Task Register Sleep Queue

7. Initialization

8. Task Preemption

9. Interconnection • CPU Interface in fabric connected to PowerPC processor via Processor Local Bus (PLB). PowerPC Interrupt Handler CPU Interface SPLB plb_v46 MPLB SPLB

10. Slave Registers • Use Slave Registers to communicate with Runtime Controller. Slave Registers CPU Interface Runtime Controller Reg0 RegN

11. Task Switching void RHS_CONT_Intr_Handler(void * baseaddr_p) { Xuint32 baseaddr; Xuint32 IpStatus; Xuint32 taskInfo; baseaddr = (Xuint32) baseaddr_p; IpStatus = RHS_CONT_mReadReg(baseaddr, RHS_CONT_INTR_IPISR_OFFSET); if (IpStatus) { taskInfo = RHS_CONT_mReadSlaveReg0(baseaddr, 0); // switch task. } }

12. Interrupt Delay • Important to keep delay minimal. • Long interrupt handling delay would render use of hardware scheduler pointless.

13. EDF Simulator • Written in C# • Used to benchmark our hardware • Gather data on the performance aspects of a software implementation of the EDF Scheduling algorithm • # tasks • utilization • # preemptions • # context switches

14. Simulator Data

15. Simulator Data # Tasks v. % Scheduler Time # Tasks v. # of Preemptions

16. Current Project Status What has been done? • Design and Implementation of priority queues • Block RAM module, which will be the task table. • Controller and Timer Module. In Progress: • CPU interface unit • Software to simulate context switching

17. Future Work Implement Dynamic Scheduling Algorithms Dynamic scheduling algorithms like slack stealing algorithmwhich has large scheduler overhead could be implemented . Reduce processor power consumption Processor consumes considerable power to run the scheduler even when there are no tasks in the system. A low power scheduling co-processor can be used to put the processor in deep sleep mode when no active tasks are present in the system.

18. References • P. Kuacharoen, M. Shalan, V. Mooney, “A Configurable Hardware Scheduler for Real-Time Systems” Center for Research on Embedded Systems and Technology School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, Georgia 30332, USA. • S. Saez, J. Vila and A. Crespo, “A hardware Scheduler for Complex Real-Time Systems,” ISIE, pp. 43-48, 1999. • S. Moon, J. Rexford and K. Shink, “Scalable hardware priority queue architectures for high-speed packet switches,” IEEE Transactions on Computer, vol. 49, no. 11, pp. 1215-1227, November 2000.

19. Questions/Comments/Suggestions?