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The Design of Asynchronous Memory Management Unit

The Design of Asynchronous Memory Management Unit. Chris Myers Alain Martin Computer System Lab. CS Dept. Stanford University Cal Tech. Asynchronous Memory Management Unit. What is a MMU?

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The Design of Asynchronous Memory Management Unit

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  1. The Design of Asynchronous Memory Management Unit Chris Myers Alain Martin Computer System Lab. CS Dept. Stanford University Cal Tech

  2. Asynchronous Memory Management Unit • What is a MMU? • 16 bit virtual address ==> a 24 bit physical address. • ma (memory address) ra (real address)

  3. Memory Management Unit 16 bit virtual address + 8-bit segmentation register ==> a 24 bit physical address. sr: Segementation Read register (FFFF) sw: Segementation Write register (FFFE)

  4. Asyn Memory Management Unit • Six Operations: • a. Read from/Write to sr (lower 8-bit data) • b. Read from/Write to wr (lower 8-bit data) • c. Read from/Write to memory (16-bit data)

  5. Asyn Memory Management Unit • 4 control signals: • a. MDl: memory data load (mem or Seg Reg==>CPU) • b. MDs: memory data store (CPU==>mem or Seg Reg) • c. MSl: memory storage load. • d. MSs: memory storage store.

  6. Memory Load • Wait for communication on MDl port • Do memory address comparison • ma=FFFEh (load from wr) • ma=FFFFh (load from sr) • otherwise load from memory. • Put sr on real address bus (ra=sr) • Request memory load from Memory Interface • (initiate a communication on MSl) • Wait until load is acknowledged then complete • communication on MDl port

  7. Store Seg. Read Register • Wait for communication on MDs port • Do memory address comparison • check ma=FFFFh • Put value from data bus into the sr register • Complete communication on MDs port

  8. Design Flow

  9. CSP Specification of MMU Load Store load from sr register load from sw register load from memory write to sr register write to sw register write to memory

  10. Optimizing CSP Specification • Logic: • Time:

  11. Optimizing CSP Specification

  12. Process Decomposition • Control path:

  13. Process Decomposition • Datapath: • A. comparator: • B. Registers:

  14. Memory Data Load Cycle

  15. Handshaking Expansion

  16. Handshaking Expansion

  17. Handshaking Expansion

  18. Handshaking Expansion

  19. Handshaking Expansion • Reshuffling

  20. Production Rule Expansion • Load data from sr register: Guard Strengthening: Make the order of transitions confirm with CSP specification.

  21. PR Implementation

  22. Handshaking Expansion:datapath • Datapath: • Reshuffling:

  23. PR Implementation: datapath • PADIN: • single-rail memory address => dual-rail memory address

  24. PR Implementation: datapath • determines if bits ma15-ma1 are all high.

  25. PR Implementation: datapath • determines if bits ma15-ma1 are all high.

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